Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1998-11-12
2004-08-17
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S301000, C257S302000, C257S501000, C257S510000, C257S797000, C438S207000, C438S218000, C438S219000, C438S294000, C438S427000
Reexamination Certificate
active
06777772
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having an improved shape of trenches formed in chip areas of a semiconductor wafer. Further, the present invention relates to a semiconductor device having an improved shape of trenches that define the peripheries of chip areas of a semiconductor wafer, as well as to manufacturing methods of those semiconductor devices.
2. Background Art
FIGS.
5
(
a
) through
5
(
c
) are sectional views showing the main parts of a semiconductor wafer in a conventional manufacturing process. Specifically, FIG.
5
(
a
) is a sectional view of a trench formed in a central portion of the wafer. FIG.
5
(
b
) is a sectional view of a trench formed at a peripheral portion of the wafer. FIG.
5
(
c
) is a sectional view schematically showing how a sputtering film peels off in a peripheral portion of the wafer.
In FIGS.
5
(
a
) through
5
(
c
), reference numeral
1
denotes a trench formed in a semiconductor wafer
10
;
4
, a sputtering particle for formation of a sputtering film;
5
, a sputtering film that is so formed as to be continuous in an area bridging the surfaces of chip areas
2
and the inside surface of the trench
1
; and
6
, an interlayer insulating film.
As shown in FIG.
5
(
a
), the sputtering film
5
is formed uniformly on a pattern of the trenches
1
in the central portion of the wafer
10
. On the other hand, as shown in FIG.
5
(
b
), the sputtering particles
5
are incident on the wafer
10
obliquely in its peripheral portion, so that the resulting sputtering films formed on side walls
1
a
and
1
b
have different thickness. Since a thinner portion of the sputtering film
5
is less resistant to stress or the like, film peeling is prone to occur as shown in FIG.
5
(
c
). That is, a coverage failure of the sputtering film
5
and a resulting film peeling are prone to occur.
FIGS.
6
(
a
) and
6
(
b
) show a plural chip areas on a semiconductor wafer and trenches formed at the peripheries of each chip area. Specifically, FIG.
6
(
a
) is a plan view of a part of a semiconductor wafer and FIG.
6
(
b
) is a sectional view of a trench.
As shown in FIG.
6
(
a
), the peripheries of chip areas
2
are defined by trenches
1
. Reference numeral
3
denotes dicing lines. The surface of a semiconductor wafer
10
is sectioned by the dicing lines
3
extending in the vertical and horizontal directions, and each section becomes a chip area
2
. Trenches
1
are formed at the boundaries between the chip areas
2
and the dicing lines
3
.
FIG.
6
(
b
) shows a sectional shape of one of the trenches
1
. In this example, interlayer insulating films
6
are formed in three layers on the semiconductor wafer
10
. The trench
1
is formed through the interlayer insulating films
6
and sputtering films
5
are formed thereon. Reference numerals
7
and
8
denote first and second metal layers, respectively, and numeral
9
denotes a field insulating film.
After semiconductor circuits are formed in the respective chip areas
2
, the semiconductor wafer
10
is diced along the dicing lines
3
and is thereby divided. The pattern of the trenches
1
that surround the chip areas
2
is provided to prevent a crack from reaching the inside of a chip area
2
during dicing. Therefore, the trenches
1
are formed for each interlayer insulating film
6
as shown in FIG.
6
(
b
).
As described above, in conventional semiconductor wafers, the trenches
1
that surround the chip areas
2
are formed straightly, and their confronting side walls extend also straightly when viewed in a plan view. With a pattern of such trenches extending straightly, it is considered that the peeling of the sputtering film
5
as described in connection with FIG.
5
(
c
) is very prone to occur.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems in the conventional art, and an object of the invention is therefore to provide a semiconductor device and a manufacturing method thereof which can prevent a sputtering film from peeling off due to a coverage failure.
The present invention provides a semiconductor device comprising at least a chip area formed on a major surface of a semiconductor wafer. A trench is formed in the chip area so that outlines of side walls of the trench have recesses or protrusions. Further, a sputtering film is formed so as to be continuous in an area bridging a surface of the chip area and an inside surface of the trench.
According to another aspect of the present invention, there is provided a semiconductor device comprising a plurality of chip areas formed on a major surface of a semiconductor wafer. A plurality of trenches are formed at a periphery of each chip area so that outlines of side walls of the trench have recesses or protrusions. Further, a sputtering film is formed so as to be continuous in an area bridging a surface of the chip area and an inside surface of the trench.
In another aspect, in each of the above semiconductor devices, the recesses or protrusions of one of the confronting side walls of the trench may be facing protrusions or recesses of the other side wall.
The protrusions of one of the confronting side walls may extend into the recesses of the other side wall.
The plan-view shape of the recesses or protrusions may be a part of one of a rectangle, a triangle, and a circle.
According to another aspect of the present invention, in a manufacturing method of a semiconductor device, trenches are formed to define chip areas on a surface of a semiconductor substrate, and the outlines of the side walls of each of the trenches are formed to have recesses or protrusions. A sputtering film is formed so as to be continuous in an area bridging a surface of each of the chip areas and an inside surface of each of the trenches. Thereafter, the semiconductor substrate is diced along lines outside the trenches.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
REFERENCES:
patent: 4502913 (1985-03-01), Lechaton et al.
patent: 4962061 (1990-10-01), Takata
patent: 5094973 (1992-03-01), Pang
patent: 5449630 (1995-09-01), Lur et al.
patent: 5662768 (1997-09-01), Rostoker
patent: 6137152 (2000-10-01), Wu
patent: 6143620 (2000-11-01), Sharan et al.
patent: 6147857 (2000-11-01), Worley et al.
patent: 05226465 (1993-03-01), None
patent: 5-152433 (1993-06-01), None
Murata Naofumi
Ohno Takio
Taya Masatoshi
McDermott Will & Emery LLP
Ortiz Edgardo
Renesas Technology Corp.
Wilson Allan R.
LandOfFree
Semiconductor device having improved trench structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having improved trench structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having improved trench structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3338201