Semiconductor device having improved interlevel conductor insula

Details Semiconductor device having improved interlevel conductor insula Semiconductor device having improved interlevel conductor insula

1980-05-02

1982-10-26

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29578, 148187, 357 23, 357 41, 357 91, H01L 2170, H01L 2126

Patent

active

043560407

ABSTRACT:
A semiconductor device and method of manufacture employs an improved insulating layer to laterally separate conductive layers or regions. A relatively thick insulating layer is anisotropically patterned to form an electrode having a thick insulating layer on its side walls. Subsequently defined conductive regions are separated from the electrode by a distance determined by the thickness of the insulating layer. In devices requiring multiple level polycrystalline silicon electrodes, shorts between electrodes are reduced; in MOS devices, operating parameters are improved due to decreased overlap of the gate electrode over the source or drain region, decreased contamination of the gate electrode during manufacture, and more uniform gate oxide definition along the active channel between the source and drain.

REFERENCES:
patent: 3996658 (1976-12-01), Takei et al.
patent: 4112575 (1978-09-01), Fu et al.
patent: 4131906 (1978-12-01), Kinoshita
patent: 4149307 (1979-04-01), Henderson
patent: 4182023 (1980-01-01), Cohen et al.
patent: 4210473 (1980-07-01), Takagi et al.
patent: 4213139 (1980-07-01), Rao
patent: 4251571 (1981-02-01), Garbarino et al.

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