Semiconductor device having improved coverage with increased wir

Details Semiconductor device having improved coverage with increased wir Semiconductor device having improved coverage with increased wir

1994-09-29

1996-09-10

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

257758, 257774, H01L 2348

Patent

active

055548644

ABSTRACT:
In a semiconductor device having a multilayer wiring, first and second lower wiring sections are formed on a base insulating film. An interlayer insulating layer covers the first and the second lower wiring sections. In the interlayer insulating layer, first and second contact holes are bored so as to reach the first and the second lower wiring sections, respectively. In the first and the second contact holes, first and second conductors are embedded so as to connect with the first and the second lower wiring sections, respectively. Formed on an upper surface of the interlayer insulating layer, a first upper wiring section interconnects with the first lower wiring section via the first conductor. The first upper wiring section has an upper surface and a side surface on which an upper insulating film and a side-wall insulating film are formed. Formed on an upper surface of the second conductor, a second upper wiring section covers an upper surface of the interlayer insulating layer so as to interconnect with the second lower wiring section via the second conductor. The second upper wiring section overlies the first upper wiring section with the second upper wiring section isolated from the first upper wiring section by the upper insulating film and the side-wall insulating film.

REFERENCES:
patent: 5103288 (1992-04-01), Sakamoto et al.
patent: 5179427 (1993-01-01), Nakayama et al.
A. Shinohara et al., "A New Self-Aligned Contact Technology for LDD MOS Transistors", Extended Abstracts of the 17th Conference on Solid State Devices and Materials, Tokyo, 1985, pp. 29-32.

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