Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2000-06-29
2002-01-22
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S750000, C257S758000, C257S760000
Reexamination Certificate
active
06340844
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, such as an IC or a LSI device, having contact holes. More particularly, the present invention relates to a semiconductor device in which the depth of a contact hole is controlled in the event the contact hole is offset from a lower conducting line. The present invention further relates to a method of manufacturing the contact holes, and more particularly, to a method of controlling the etching depth of a contact hole in the event of a contact hole is offset from a lower conducting line.
2. Background Art
In association with miniaturization of a semiconductor element, it has become difficult to ensure a sufficient overlay margin between a contact hole and a lower conducting line or a like conducting element. For this reason, as in the case of a conventional semiconductor device shown in
FIGS. 9 and 10
, a contact hole happens to be offset from a lower electrode with which the contact hole is to be electrically connected. At this time, if the depth of etching is great, the contact hole may reach a lower electrode with which the contact hole should not be connected; that is, a lower electrode or a substrate.
FIGS. 9 and 10
are cross-sectional views showing example conventional semiconductor devices in which a contact hole is offset from a conducting line with which the contact hole is to be connected.
In
FIGS. 9 and 10
, reference numeral
101
designates a semiconductor substrate;
102
designates an element isolation region;
103
designates a first conducting line or a first electrode line;
104
designates an interlayer dielectric film to be formed on the first conducting line
103
;
107
designates a second conducting line or a second electrode line;
108
designates an interlayer dielectric film to be formed on the second conducting line
107
;
109
designates a photoresist
5
mask to be used for forming a contact hole;
110
designates a contact hole pattern; and
111
designates the extra etching amount “r,” which would result when the contact hole is brought out of alignment with the second conducting line
107
.
In the case of the conventional semiconductor device shown in
FIG. 9
, a sufficient margin between the first conducting line
103
and the second conducting line
107
; i.e., a sufficient layout interval between these conducting lines, is ensured for counting occurrence of an offset of the contact hole
110
. Further, in the case of the conventional semiconductor device shown in
FIG. 10
, a pattern for the first conducting line
103
is designed to be sufficiently wide so as to prevent the contact hole
110
from being offset from the first conducting line
103
. Both methods pose a problem of an increase in the area of a chip.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve such a drawback of the background art and is aimed at providing a semiconductor device which has a contact hole of which depth is controlled when the contact hole is offset from a lower conducting line. The present invention is further aimed at providing a method of controlling the depth of etching in the event of a contact hole being offset from a lower conducting line during the course of etching of the contact hole.
According to one aspect of the present invention, a semiconductor device comprises a semiconductor substrate and a interlayer insulation film formed on the semiconductor substrate. A first conductor line formed at a relatively lower position within an interlayer dielectric film laid. A second conductor line formed at a relatively higher position within the interlayer dielectric film. An etching stopper film is formed within the interlayer dielectric film at an intermediate position between the first and second conductor lines, and the etching stopper film has an etch selectivity differing from that of the interlayer dielectric film for a predetermined etching condition. A contact hole is formed in the interlayer dielectric film so as to extend from the surface of the interlayer dielectric film to reach the second conducting line, and the offset portion of the contact hole from the second conducting line extends toward the etching stopper film, and terminates at longest at the etching stopper film. Further, a contact conductor is filled in the contact hole.
According to another aspect of the present invention, a semiconductor device comprises a semiconductor substrate and
an interlayer insulation film formed on the semiconductor substrate. A first conductor line is formed at a relatively lower position within an interlayer dielectric film laid. A second conductor line is formed at a relatively higher position within the interlayer dielectric film. An etching stopper film is formed within the interlayer dielectric film at a position higher than the second conductor line, and the etching stopper film has an etch selectivity differing from that of the interlayer dielectric film for a predetermined etching condition. A contact hole is formed in the interlayer dielectric film so as to extend from the surface of the interlayer dielectric film to reach the second conductor line through the etching stopper film, and the offset portion of the contact hole from the second conductor line extends toward the semiconductor substrate, and terminates before reaching the semiconductor substrate. Further, a contact conductor is filled in the contact hole.
According to another aspect of the present invention, a semiconductor device comprises a semiconductor substrate and an interlayer insulation film formed on the semiconductor substrate. A first conductor line is formed at a relatively lower position within an interlayer dielectric film laid. A second conductor line is formed at a relatively higher position within the interlayer dielectric film. A first etching stopper film is formed within the interlayer dielectric film at an intermediate position between the first and second conductor lines. A second etching stopper film is formed within the interlayer dielectric film at a position higher than the second conductor line. The first and second etching stopper films have an etch selectivity differing from that of the interlayer dielectric film for a predetermined etching condition. A contact hole is formed in the interlayer dielectric film so as to extend from the surface of the interlayer dielectric film to reach the second conducting line through the second etching stopper film, and the offset portion of the contact hole from the second conducting line extends toward the first etching stopper film, and terminates at longest at the first etching stopper film. Finally, a contact conductor is filled in the contact hole.
Other and further objects, features and advantages of the invention will appear more fully from the following description
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