Semiconductor device having hierarchized bit lines

Details Semiconductor device having hierarchized bit lines Semiconductor device having hierarchized bit lines

2007-08-21

2007-08-21

Phan, Trong (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S154000, C365S156000

Reexamination Certificate

active

10952824

ABSTRACT:
A semiconductor device having hierarchized bit lines including an upper-layer bit line and a lower-layer bit line, includes at least one memory cell array to which the lower-layer bit line is connected and a selection transfer gate having an NMOS switching transistor and a PMOS switching transistor to connect the lower-layer bit line to the upper-layer bit line. The NMOS switching transistor and the PMOS switching transistor of the selection transfer gate are arranged opposite to each other in a column direction to sandwich the memory cell array.

REFERENCES:
patent: 5724292 (1998-03-01), Wada
patent: 5793664 (1998-08-01), Nagata et al.
patent: 6359803 (2002-03-01), Tanaka
patent: 6515887 (2003-02-01), Fujimoto
patent: 6839268 (2005-01-01), Osada et al.
patent: 6930941 (2005-08-01), Nakase
patent: 7085178 (2006-08-01), Proebsting et al.
patent: 7-326186 (1995-12-01), None
patent: 2004-103159 (2004-04-01), None

Affiliated with

Also associated with

Rating

Semiconductor device having hierarchized bit lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having hierarchized bit lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having hierarchized bit lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3845008