Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
1999-07-15
2002-05-07
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S546000, C365S226000
Reexamination Certificate
active
06384674
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, it relates to a semiconductor device having a hierarchical power supply line structure.
2. Description of the Prior Art
The withstand voltage of a transistor is reduced as the transistor is refined, and hence the operating voltage must inevitably be lowered. For battery driving which is prerequisite for a portable device, an operation under a low voltage and low power is essential.
When the operating voltage is lowered, however, the operating speed is reduced in general. In order to implement a low-voltage operation without reducing the operating speed, therefore, the threshold voltage of a MOS transistor must be lowered. If the threshold voltage is excessively lowered, however, the transistor cannot be sufficiently cut off but an unnegligible subthreshold current flows also when the transistor is in an OFF state. Thus, low power consumption, which is the maximum feature of a conventional CMOS circuit, is lost.
FIG. 44
is a circuit diagram showing the structure of an invertor
1500
in a conventional semiconductor device.
Referring to
FIG. 44
, the invertor
1500
includes a P-channel MOS transistor
1501
having a gate receiving an input signal IN and a source coupled to a power supply potential Vdd, and an N-channel MOS transistor
1502
having a gate receiving the input signal IN, a source coupled to a ground potential Vss and a drain connected to that of the P-channel MOS transistor
1501
.
The drain of the N-channel MOS transistor
1502
outputs an output signal OUT. Assuming that Vt represents the threshold voltage of the N-channel MOS transistor
1502
, the operating speed of the transistor
1502
is substantially in inverse proportion to Vdd−Vt. In order to suppress reduction of the operating speed, therefore, the threshold voltage Vt must be reduced in response to reduction of the power supply potential Vdd.
If the threshold value Vt is excessively lowered, however, an unnegligible subthreshold current IL flows in the N-channel MOS transistor
1502
also when a potential 0 V is supplied as the input signal IN.
FIG. 45
illustrates the relation between a gate-to-source voltage VGS and a drain current IDS of the N-channel MOS transistor
1502
.
This figure shows change of the drain current IDS following change of the gate-to-source voltage VGS around the threshold voltage Vt. The drain current IDS is logarithmically plotted on the vertical line.
Referring to
FIG. 45
, it is assumed that the gate-to-source voltage VGS reaches the threshold voltage Vt when a constant current
10
flows in the transistor
1502
in a line
1504
. Consider the case of employing an N-channel MOS transistor having a lower threshold voltage Vt
2
in place of the threshold voltage Vt, to be usable under a low power supply voltage.
A line
1506
shows the relation between the drain current IDS and the gate-to-source voltage VGS of this N-channel MOS transistor. Comparing the values of the drain currents IDS on the lines
1504
and
1506
when the gate-to-source voltages VGS are zero, the value of the drain current IDS rises from IL to IL
2
. Therefore, the subthreshold current cannot be neglected following high integration and reduction of the power supply voltage, and increase of a standby current causes a critical problem in a portable device driven by a battery.
FIG. 46
is a circuit diagram showing an invertor
1510
reducing a subthreshold current by switching a source voltage proposed in general.
Referring to
FIG. 46
, the invertor
1510
includes an invertor
1511
having a power supply node coupled with a power supply potential Vdd and a ground node connected to a node N
100
for receiving an input signal IN and outputting an output signal OUT, and an N-channel MOS transistor
1516
having a gate receiving a control signal SCRC, a drain connected to the node N
100
and a source coupled to a ground potential Vss.
The invertor
1511
includes a P-channel MOS transistor
1512
having a gate receiving the input signal IN, a source connected to the power supply node and a drain connected to an output node, and an N-channel MOS transistor
1514
having a gate receiving the input signal IN, a source connected to the node N
100
and a drain connected to the output node.
FIGS. 47A and 47B
are diagrams for illustrating types of transistors.
FIG. 47A
is a diagram for illustrating the symbol of a transistor
1518
having a high threshold voltage, and
FIG. 47B
is a diagram for illustrating the symbol of a transistor
1520
having a low threshold voltage.
Referring to
FIGS. 47A and 47B
, it is assumed that the symbol of the transistor
1518
shown in
FIG. 47A
stands for a transistor having a high threshold voltage, and the symbol of the transistor
1520
shown in
FIG. 47B
stands for a transistor having a low threshold voltage.
Referring again to
FIG. 46
, this circuit renders the N-channel MOS transistor
1516
conductive, sets the potential VN of the node N
100
at the ground potential Vss and lets the invertor
1511
perform an ordinary logic operation with the control signal SCRC in ordinary operation.
When the potential supplied by the input signal IN is at a low level, the P-channel MOS transistor
1512
is rendered conductive while the N-channel MOS transistor
1514
is rendered non-conductive, and the output potential of the output signal OUT goes high. In this case, a subthreshold current flows in the non-conductive N-channel MOS transistor
1514
and a current resulting from the subthreshold current flows from the power supply node supplied with the power supply potential Vdd to the ground node supplied with the ground potential Vss.
When the input level of the input signal IN is high, on the other hand, the P-channel MOS transistor
1512
is rendered non-conductive while the N-channel MOS transistor
1514
is rendered conductive, and the level of the output signal OUT goes low. In this case, a subthreshold current flows in the non-conductive P-channel MOS transistor
1512
, to flow from the power supply node to the ground node. Thus, power is unavoidably consumed by the subthreshold current in an ordinary operating state.
When employing this circuit during a period when it is recognized that input logic is previously fixed, e.g., during a standby period when the chip is in a standby state, power consumption by the subthreshold current can be reduced.
Assuming that the input signal IN for this circuit goes low in the standby state, the P-channel MOS transistor
1512
is rendered conductive while the N-channel MOS transistor
1514
is rendered non-conductive. At this time, the output signal OUT is at a high level.
When switching the control signal SCRC from a high level to a low level for switching control from an operating state to the standby state, the N-channel MOS transistor
1516
is rendered non-conductive. The absolute value of the threshold voltage of the N-channel MOS transistor
1516
is greater than that of the N-channel MOS transistor
1514
, and hence a subthreshold current flowing through the N-channel MOS transistor
1516
is remarkably smaller than that flowing in the N-channel MOS transistor
1514
.
Thus, a leakage current flowing from the power supply node to the ground node depends on the subthreshold current of the N-channel MOS transistor
1516
, and hence power consumption by the subthreshold current can be reduced in the standby state.
Despite the high threshold voltage of the N-channel MOS transistor
1516
, the operating speed of the invertor
1511
is not influenced when the N-channel MOS transistor
1516
is in a conductive state. Further, the speed for switching from the operating state to the standby state may not be so high as the operating speed of the invertor
1511
, and hence no problem arises even if the N-channel MOS transistor
1516
has a high threshold voltage and a slightly low operating speed.
When the input signal IN is at a low level, as hereinabove described, the circuit can be set in the standby
Hidaka Hideto
Ishikawa Masatoshi
Ooishi Tsukasa
Tanizaki Hiroaki
Tomishima Shigeki
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tra Quan
Tran Toan
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