Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-10-06
2003-09-30
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S751000, C257S760000, C257S765000
Reexamination Certificate
active
06627996
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor device having a memory function, a logic function and various functions specific to semiconductor materials, and a fabrication process thereof. More specifically, the invention relates to a multilayer interconnection structure of such semiconductor device and a fabrication process thereof.
2. Description of the Related Art
In conjunction with the refinement and increase of package density of semiconductor integrated circuits in recent years, refinement and employment of multilayer wiring structures has also progressed rapidly. In a logic type semiconductor device, since shortening of a propagation delay of a signal is essential, reduction of the dielectric constant of an interlayer insulation layer is demanded. Therefore, it has been studied to introduce a fluorine containing gas using a high density plasma CVD (Chemical Vapor Deposition) device (HPD-CVD) to deposit SiOF (dielectric constant approximately equal to 3.3) as a low dielectric constant layer.
When the SiOF layer as the low dielectric constant layer is used, it becomes possible to satisfactorily fill the space between wirings even when this space is less than or equal to 0.25 m. It is not possible to fill such small spaces in the case of a Si oxide layer formed by a parallel plate plasma CVD method (PE-CVD method) using TEOS (tetraethoxy silane) or the like, which has been widely used conventionally, as a material gas.
On the other hand, in addition to the HDP-CVD method, there is a method for forming the SiOF layer by addition of an etching type gas containing fluorine upon forming the Si oxide layer by the foregoing parallel plate plasma CVD method (PE-CVD method) (for example, Japanese Unexamined Patent Publication (Kokai) No. Heisei 6-302593). Even in this method, since etching is progressed simultaneously with deposition of the layer, good burying ability can be achieved so that the SiOF layer can be buried even in a wiring interval which is smaller in comparison with Si oxide layer.
For good burying ability of SiOF in a widely used product having closely spaced wiring patterns, study has been made of a memory type device, such as a dynamic random access memory (DRAM).
As wiring of the semiconductor device, an Al alloy has been widely used. However, upon formation of Al wiring, TiN layer as an anti-reflection layer preventing surface reflection during lithography, is frequently formed. A structure where the SiOF layer is directly deposited on a wiring having the upper surface covered with TiN, is preferred in view of lowering of the dielectric constant. However, due to low bonding ability between TiN and the SiOF layer, a problem is encountered in that peeling is easily caused at the interface between the layers. While burying ability becomes higher at higher fluorine concentration in the SiOF layer, the problem of peeling becomes more significant at higher fluorine concentration in the SiOF layer.
Separately from the foregoing problem, in the SiOF layer having high fluorine concentration, fluorine may be dispersed during a process, such as heat treatment or the like, to possibly cause corrosion by reaction with Al type wiring. For the measure of this problem, there has been proposed a method to grow Si oxide layer before growth of the SiOF layer (for example, Japanese Unexamined Patent Publication No. Heisei 7-74245). Section of the prior art employing this method is shown in FIG.
6
. On a BPSG layer
602
of a Si semiconductor substrate
601
, a Si oxide layer
604
not added fluorine is formed in a thickness of 100 nm by a PE-CVD method, on an Al wiring
603
, using TEOS and O
2
. By forming the SiOF layer
605
in a thickness of 500 nm is formed on Si oxide layer
604
using TEOS, O
2
and NF
3
, interval between Al wiring is filled. In this method, diffusion of fluorine in the SiOF layer is prevented by Si oxide layer and bonding ability of the anti-reflection layer TiN and the SiOF layer can be improved.
However, by growth of Si oxide layer, overhang shape
606
is formed between the wiring as shown in
FIG. 6
to cause difficulty in burying the SiOF layer in the fine wiring
607
. Particularly, coverage is lowered in the narrow space portion less than or equal to 0.25 &mgr;m to cause void
608
or so forth between the wiring to be a cause of degradation of reliability of the wiring. Also, due to double the layer structure of the Si oxide layer and the SiOF layer having a high relative dielectric constant, the dielectric constant becomes higher in comparison with a single SiOF layer.
The problems in the prior art is low reliability of wiring due to the possibility of corrosion of Al type wiring by fluorine diffusion and the occurrence of peeling in the interface with TiN when the SiOF layer is directly grown on a first wiring having TiN as the anti-reflection layer.
The reason is that a fluoride of Ti is formed on the surface of the TiN by the SiOF grown layer or fluorine in the SiOF layer. There is a low bonding ability between the fluoride and the SiOF layer, and furthermore, since the Al type wiring and plasma SiOF oxide layer are in direct contact, fluorine may be diffused by heat treatment or so forth to react with Al type substance.
The second problem is that when a Si oxide layer is formed below the SiOF layer, despite of the fact that the SiOF layer is used as an insulation layer, the burying ability to the narrow wiring space portion is not high. Furthermore, it is not possible to achieve satisfactory lowering of the dielectric constant as a whole of the insulation layer.
The reason is that Si oxide layer is deposited immediately before deposition of the SiOF layer. Coverage of Si oxide layer is not good and forms an overhang like configuration to lower the burying ability of the subsequently formed the SiOF layer within the wiring space portion, and by stacking with Si oxide layer having high relative dielectric constant, dielectric constant of the overall interlayer insulation layer cannot be lowered satisfactorily.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device which can improve bonding ability with a metal wiring, prevent corrosion of wiring, improve burying ability between fine wiring, achieve low dielectric constant in overall interlayer insulation layer and achieve speeding up of the device with making a capacity between wiring small.
According to one aspect of the present invention, a semiconductor device comprises:
wiring formed on a semiconductor substrate by etching;
an insulation layer serving as a mask for etching in formation of the wiring, the insulation layer being formed only on the surface above the wiring via an anti-reflection layer; and
a Si oxide layer containing fluorine and burying the anti-reflection layer and the insulation layer therein.
The insulation layer on the wiring may be an Si oxide layer or an Si nitride layer.
The anti-reflection layer on the wiring may be formed of a refractory metal or a compound thereof, such as any one of Ti, W, TiN and TiW or a laminated structure thereof. A major component of the wiring may be Al or Cu.
According to another aspect of the present invention, a fabrication process of a semiconductor device comprises:
a metal layer forming step of forming a metal layer to be a base of wiring on a semiconductor substrate;
an anti-reflection layer forming step of forming an anti-reflection layer of a refractory metal or compound thereof, on the metal layer;
an insulation layer forming step of forming an insulation layer on the anti-reflection layer;
an insulation layer patterning step of patterning the insulation layer;
a wiring patterning step of performing patterning of the wiring by etching the anti-reflection layer and the metal layer to be the base of the wiring with taking the patterned insulation layer as a mask with leasing the anti-reflection layer and the insulation layer on the wiring; and
an SiOF layer burying step of burying the patterned wiring with an SiOF layer a
Kishimoto Koji
Yamada Yoshiaki
Yokoyama Takashi
Foley & Lardner
Lewis Monica
NEC Electronics Corporation
Zarabian Amir
LandOfFree
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