Semiconductor device having finely configured gate electrodes

Details Semiconductor device having finely configured gate electrodes Semiconductor device having finely configured gate electrodes

1995-12-18

1997-12-16

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257412, 257647, H01L 2348

Patent

active

056989024

ABSTRACT:
There are provided: an isolation protruding upward from a semiconductor substrate in an active region; a gate electrode formed in the active region; and a pair of dummy electrodes formed to extend over the active region and the isolation and substantially in parallel with the gate electrode. Each of the gate electrode and dummy electrodes is composed of a lower film and an upper film. The lower films of the dummy electrodes are formed flush with the isolation and in contact with the side edges of the isolation. With the dummy electrodes, any gate electrode can be formed in a line-and-space pattern, so that the finished sizes of the gate electrode become uniform. This enables a reduction in gate length and therefore provides a semiconductor device of higher integration which is operable at a higher speed and substantially free from variations in finished size resulting from the use of different gate patterns.

REFERENCES:
patent: 4477962 (1984-10-01), Godejahn, Jr.
patent: 5164803 (1992-11-01), Ozaki et al.
patent: 5321291 (1994-06-01), Redwine
patent: 5440161 (1995-08-01), Iwamatsu et al.
patent: 5521419 (1996-05-01), Wakamiya et al.

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