Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-10-12
2003-02-18
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S358000, C257S359000, C257S363000, C257S379000, C257S380000
Reexamination Certificate
active
06522007
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a technique of arranging dummy patterns for metal CMP (Chemical Mechanical Polishing).
2. Description of the Background Art
With refinement of patterns of semiconductor devices, a metal CMP technique has been used as a technique of planarizing interlayer insulating films in multilayer interconnections (the first background art: “The State of The Art and Trend of Metal CMP”, Applied Physics Vol. 68, No. 11, 1999, pp. 1243-1246).
Further, according to the second background art (Japanese Patent Application Laid Open Gazette No. 09-306996), the third background art (Japanese Patent Application Laid Open Gazette No. 10-256255) and the fourth background art (Japanese Patent Application Laid Open Gazette No. 2000-338646), since use of the metal CMP in a case where patterns have large difference in density is likely to cause excessive polishing in a portion of small pattern density (less dense portion), it is proposed that dummy patterns should be provided in a portion of small pattern density besides normal patterns which are originally needed so as to avoid the excessive polishing in the less dense portion for prevention of pattern removal and achieve a further polarization of interlayer insulating films. A process of forming such dummy patterns depends on design rules in layout design of wiring pattern and the amount of data in formation of mask pattern.
Furthermore, the fifth background art (Japanese Patent Application Laid Open Gazette No. 2000-007107) proposes to form dummy patterns besides normal patterns for prevention of excessive erosion caused by use of the metal CMP.
When a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a relatively long gate length (e.g., about 10 &mgr;m) is formed on a semiconductor substrate, the pattern density in a MOSFET formation region becomes small. If the metal CMP is performed in a process of manufacturing such a semiconductor device, the metal CMP causes an excessive erosion in the MOSFET formation region and as a result, there is a possibility that a desired planeness may not be obtained. That raises necessity of arranging metal dummy patterns for the metal CMP above a gate electrode of the MOSFET having a relatively long gate length.
The sixth background art (Proc. IEEE 1997 Int. Conference on Microelectronic Test Structure, Vol. 11, March 1997), however, reports that covering an upper layer of a MOS-structure transistor with a metal layer may cause deterioration in characteristics of transistors, such as deterioration in drain currents.
Therefore, formation of dummy patterns above a gate electrode causes a problem that characteristics of a plurality of MOS-structure transistors can not become uniform.
Such a problem arises not only in the MOS-structure transistors having a relatively long gate length but also in other elements. Specifically arises the problem of deterioration in characteristics of elements also when metal dummy patterns are provided above a plurality of resistive elements and metal dummy patterns are provided below an inductor.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: a semiconductor substrate; a MOS-structure transistor formed on a main surface of the semiconductor substrate, comprising a first main electrode region, a second main electrode region and a gate electrode for controlling currents flowing between the first main electrode region and the second main electrode region; an interlayer insulating film fir formed on an upper surface of the gate electrode, covering the MOS-structure transistor; and a metal dummy pattern formed on an upper surface of the interlayer insulating film and positioned above the upper surface of the gate electrode, and in the semiconductor device of the first aspect, the first main electrode region is opposed to the second main electrode region in a first direction which corresponds to a direction of gate length of the gate electrode, the first main electrode region, the second main electrode region, the gate electrode and the metal dummy pattern extend in a second direction perpendicular to the first direction, which corresponds to a direction of gate width of the gate electrode, and a geometric center of the gate electrode in the second direction coincides with a geometric center of the metal dummy pattern in the second direction.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the interlayer insulating film and the metal dummy pattern are defined as a first interlayer insulating film and a first-layer metal dummy pattern, respectively, and the semiconductor device of the second aspect further comprises: a second interlayer insulating film covering the first interlayer insulating film and the first-layer metal dummy pattern; and a plurality of second-layer metal dummy patterns formed on portions of an upper surface of the second interlayer insulating film other than a portion above the first-layer metal dummy pattern and arranged in stripes at first intervals in the first direction, and in the semiconductor device of the second aspect, each of the plurality of second-layer metal dummy patterns extends in the second direction, the first-layer metal dummy pattern and the plurality of second-layer metal dummy patterns are arranged at a second interval in a third direction perpendicular to the first direction and the second direction, and a width of each of the plurality of second-layer metal dummy patterns in the first direction is equal to that of the first-layer metal dummy pattern in the first direction.
According to a third aspect of the present invention, the semiconductor device of the second aspect further comprises: a third interlayer insulating film covering the second. interlayer insulating film and the plurality of second-layer metal dummy patterns; and a plurality of third-layer metal dummy patterns formed on portions of an upper surface of the third interlayer insulating film other than portions above the plurality of second-layer metal dummy patterns and arranged in stripes at the first intervals in the first direction, and in the semiconductor device of the third aspect, each of the plurality of third-layer metal dummy patterns extends in the second direction, one of the plurality of third-layer metal dummy patterns is positioned above the first-layer metal dummy pattern, a width of each of the plurality of third-layer metal dummy patterns in the first direction is equal to that of the first-layer metal dummy pattern in the first direction, and an interval between the plurality of second-layer metal dummy patterns and the plurality of third-layer metal dummy patterns in the third direction is equal to the second interval.
According to a fourth aspect of the present invention, the semiconductor device of the third aspect further comprises: a fourth interlayer insulating film covering the third interlayer insulating film and the plurality of third-layer metal dummy patterns; and a plurality of fourth-layer metal dummy patterns formed on portions of an upper surface of the fourth interlayer insulating film other than portions above the plurality of third-layer metal dummy patterns and arranged in stripes at the first intervals in the first direction, and in the semiconductor device of the fourth aspect, each of the plurality of fourth-layer metal dummy patterns extends in the second direction, each of the plurality of fourth-layer metal dummy patterns is positioned above a corresponding one out of the plurality of second-layer metal dummy patterns, a width of each of the plurality of fourth-layer metal dummy patterns in the first direction is equal to that of the first-layer metal dummy pattern in the first direction, and an interval between the plurality of third-layer metal dummy patterns and the plurality of fourth-layer metal dummy patterns
Kouno Hiroyuki
Kumamoto Toshio
Miki Takahiro
Satoh Hisayasu
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Thomas Tom
Tran Thien F
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