Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2007-12-28
2009-10-13
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S161000
Reexamination Certificate
active
07602224
ABSTRACT:
A delay locked loop includes: a control voltage generator configured to generate a voltage control signal having a voltage level corresponding to a phase difference between an external clock and a feedback clock; a voltage controlled delay line configured to generate a plurality of output signals by reflecting a different delay time on the external clock in response to the voltage control signal; an internal clock multiplexer configured to output one of the plurality of output signals as an internal clock in response to a skew information signal; a delay replica model configured to output the feedback clock by reflecting a delay of an actual clock/data path on the internal clock; and a skew information signal generator configured to generate the skew information signal.
REFERENCES:
patent: 6507230 (2003-01-01), Milton
patent: 6813197 (2004-11-01), Park
patent: 6989700 (2006-01-01), Kim
patent: 7103133 (2006-09-01), Jung
patent: 7154311 (2006-12-01), Lim
patent: 7170313 (2007-01-01), Shin
patent: 7397875 (2008-07-01), Primrose et al.
patent: 2006/0267649 (2006-11-01), Park et al.
patent: 11-316618 (1999-11-01), None
patent: 2004-201348 (2004-07-01), None
patent: 2005-251370 (2005-09-01), None
patent: 10-2001-0026746 (2001-04-01), None
patent: 10-2001-0091534 (2001-10-01), None
patent: 10-2003-091015 (2003-12-01), None
patent: 10-0512935 (2003-12-01), None
patent: 10-2005-0041677 (2005-05-01), None
Korean Office Action, with English translation, issued in Korean Patent Application No. KR 10-2007-0047500, mailed May 28, 2008.
Khan, Q., et al., “Techniques for On-Chip Process Voltage and Temperature Detection and Compensation”, Proceedings of the 19th International Conference on VLSI Design (VLSID '06), 2006, IEEE Computer Society.
Korean Notice of Allowance issued in Korean Patent Application No. KR 10-2007-0064134, dated Aug. 25, 2008.
Hynix / Semiconductor Inc.
Mannava & Kang P.C.
Wells Kenneth B.
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