Pulse or digital communications – Receivers – Interference or noise reduction
Reexamination Certificate
2000-11-07
2003-04-29
Pham, Chi (Department: 2631)
Pulse or digital communications
Receivers
Interference or noise reduction
C375S233000, C708S323000
Reexamination Certificate
active
06556637
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a semiconductor device, and more particularly, to a semiconductor device having a decision feedback equalizer that is used to demodulate and decode a read signal from the read head of a hard disk unit or a received signal in a fast communication apparatus.
A read channel LSI in a hard disk unit has a waveform equalizer that converts an analog signal, read from a hard disk using a read head, into a digital signal. A reception LSI in a fast communication apparatus has a waveform equalizer that demodulates and decodes a received signal.
As the recording density and the communication speed are increased, a decision feedback equalizer (DFE) that is suitable for fast operation and size reduction becomes more preferred than a PRML (Partial Response and Maximum Likelihood) type waveform equalizer.
The read channel LSI computes a timing error in phase and frequency matching and computes an amplitude error in amplifying the amplitude of an input signal in accordance with the result of a decision made by the decision feedback equalizer. More specifically, a variable gain amplifier in the read channel LSI amplifies the amplitude of the read signal and an A/D converter in the read channel LSI converts the amplified signal into a digital signal. The equalizer has a feed forward filter, an adder, a decision unit, a shift register and a feedback filter. The result of decision on the digital signal made by the decision unit is stored in the shift register whose output is fed back to the adder via a feedback equalizer.
A timing recovery PLL changes the frequency of a sampling clock to the A/D converter in accordance with the equalized output from the decision unit and the decision result from the shift register. A timing recovery loop is therefore formed which changes the frequency of sampling clock supplied to the A/D converter, i.e., changes the frequency of sampling clock in accordance with the output of the A/D converter and feeds the changed sampling clock back to the A/D converter. The timing recovery loop performs the phase and frequency matching such that the sampling clock is accurately synchronized with the read signal.
An amplitude error is computed according to the equalized output and the decision result and a control signal for adjusting the gain of the variable gain amplifier according to the computation result is generated. An auto gain control (AGC) loop is therefore formed which supplies the control signal to the variable gain amplifier. The AGC loop optimizes the gain of the variable gain amplifier such that an analog signal whose amplitude is suitable for the input of the decision feedback equalizer is supplied to the A/D converter.
The decision feedback equalizer executes waveform equalization by feeding back an old decision result stored in the shift register. Therefore, a decision error that occurs one time is likely to be propagated. When an equalization signal y(n) varies due to some factor, such as inadequate phase and frequency matching, as shown in
FIG. 1
, although the decision result “+1” is accurate, an incorrect decision result “−1” may be generated at time t1. When this decision error is propagated, the decision state cannot be returned to the original, correct decision state. Further, the error propagation affects the error computation.
Such a decision error influences the timing recovery loop and AGC loop. When a(n−1) !=a(n) where y(n) is the equalized output and a(n) is the decision result (“!=” is a symbol for comparison computation (≠)), a timing error TE(n) and an amplitude error AGCerr are acquired from the following equations 1 and 2.
TE(
n
)=(
y
(
n
)+
y
(
n
−1))×
a
(
n
−1) (1)
AGCerr=(|
y
(
n
)|−Ref) (2)
where Ref is a reference value that is preset in accordance with the amplitude needed to demodulate and decode a read signal.
As error computation is carried out using the decision result from the decision unit in this manner, the result of the timing error computation and the result of the amplitude error computation contain errors. The errors make the timing recovery PLL and AGC loop unstable.
Further, the initial sampling should not necessarily always start at the optimal sampling point or a point close to that optimal sampling point. If the phase of an analog signal is shifted by±30 degrees with respect to one cycle of preamble data, a computation result having a symbol “+” and a computation result having a symbol “−” alternately appear in the timing error computation. As a result, phase and frequency matching cannot be performed.
When the sample timing is shifted, for example, an incorrect decision result a(n), (+1, +1, −1, −1, −1, −1) , not the correct decision result (+1, +1, +1, −1, −1, −1), is generated, thus producing a timing error TE(n) having a symmetrical waveform, as shown in FIG.
2
. This timing error TE(n) causes the control amount that leads the phase of the sampling clock to coincide with the control amount that lags the phase of the read signal. This results in pseudo locking which maintains a state in which the phase of the sampling clock is shifted from the phase of the read signal, thus deteriorating the stability of the equalizer.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device having a decision feedback equalizer that stably performs waveform equalization.
In one aspect of the present invention, a semiconductor device is provided that includes a decision feedback equalizer for generating a decoded signal by eliminating intersymbol interference from sampled data generated by sampling an input signal in accordance with a clock signal. The decision feedback equalizer includes a feed forward filter for filtering the sampled data to generate filtered data, an adder, connected to the feed forward filter, for adding the filtered data and a feedback signal to generate an equalization signal. A decision unit is connected to the adder to compare the equalization signal with a predetermined reference signal to generate a decision signal. A shift register is connected to the decision unit to store the decision signal. A feedback filter is connected to the shift register and the adder to receive the decision signal stored in the shift register and generate the feedback signal. The semiconductor device matches a phase and frequency of the clock signal with a phase and frequency of the input signal using the equalization signal and the decision signal. The semiconductor device includes a replica signal generator that connected to the shift register to supply a replica signal corresponding to a predetermined decision result to the shift register in place of the decision signal at a time of phase and frequency matching.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 5455844 (1995-10-01), Ishikawa et al.
patent: 5703904 (1997-12-01), Langberg
patent: 6178198 (2001-01-01), Samueli et al.
patent: 6341360 (2002-01-01), Abdelilah et al.
patent: 6370191 (2002-04-01), Mahant-Shetti et al.
patent: 2000-149458 (2000-05-01), None
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Pham Chi
Tran Khai
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