Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-04-23
2004-07-06
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S758000, C257S776000
Reexamination Certificate
active
06759747
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor substrate, and more particularly, the present invention relates to a damascene interconnection structure.
This application is a counterpart of Japanese application Serial Number 163304/1998, filed Jun. 11, 1998, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
In general, it is difficult to form a pattern by etching a Copper (Cu) interconnection. In a formation of the Cu interconnection, an insulating layer such as SiO
2
or BPSG is formed on a semiconductor substrate. Then, a recess is formed in the insulating layer so as to shape the Cu interconnection. Then, Cu is buried in the recess. As a result, the Cu interconnection buried in the recess is a so-called damascene interconnection, which is formed on the semiconductor substrate.
Such a damascene interconnection is formed as shown in FIG.
1
A-FIG.
1
D. FIG.
1
A-
FIG. 1D
are cross sectional views showing a damascene interconnection structure of a conventional art.
A first interconnection pattern recess is formed using photolithography technique and etching technique in a first SiO
2
film
12
having a thickness of 1 &mgr;m on the semiconductor substrate
10
. Then, a barrier layer
16
such as a TiN is formed on the first SiO
2
film
12
in the first interconnection pattern recess. Then Cu is formed on the entire surface and the Cu is polished with alkaline solution having a colloidal-silica, so called CMP (chemical mechanical polishing) method. As a result, a first interconnection including a main interconnection
19
which is made up of the Cu, as shown in
FIG. 1A. A
second SiO2 film
22
having a thickness of 1 &mgr;m is formed on the first SiO2 film
12
where the first interconnection
18
was formed. Then, a through hole
55
is formed in the second SiO2 film
22
so that a center portion of an upper surface of the first interconnection
18
is exposed, as shown in FIG.
1
B.
A second interconnection pattern recess
24
is formed so that a predetermined portion of the through hole
55
is remained. Then, a barrier layer
26
such as TiN is formed in the remained through hole
55
and the second interconnection pattern recess
24
, as shown in FIG.
1
C.
Then, Cu is formed on the entire surface using sputtering technique, and the Cu is polished using the CMP method. As a result, a second interconnection
28
including a main interconnection
29
which is made up of the Cu, as shown in FIG.
1
D.
In the conventional art of the method for forming the interconnections, it is desirable to avoid a problem wherein the Cu transfers from a portion connected to the second interconnection due to electromigration, whereby a void is formed at the connected portion, and the first interconnection is disconnected from the second interconnection.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device that can avoid the above noted problem so that the Cu transfers from a portion connected to the second interconnection due to electromigration, whereby a void is formed at the connected portion, and the first interconnection is disconnected to the second interconnection.
According to one aspect of the present invention, for achieving the above object, there is provided a semiconductor device comprising: a first insulating layer having a through hole; a first interconnection comprised a first conductive layer, a first barrier layer, and a first main interconnection; the first conductive layer formed on the first insulating layer in the first through hole; the first barrier layer formed on the first conductive layer; the first main interconnection formed on the first barrier layer so as to bury the through hole; and a second interconnection connected to one of the first conductive layer and the first barrier layer.
According to another aspect of the present invention, for achieving the above object, there is provided a semiconductor device comprising: a first insulating layer having a through hole; a first connection comprised of a first conductive layer, a first barrier layer, and a first main interconnection; the first conductive layer formed on the first insulating layer in the first through hole; the first barrier layer formed on the first conductive layer; the first main interconnection formed on the first barrier layer so as to bury the through hole; and a second interconnection connected to one of an edge portion of the first conductive layer exposed from an upper surface of the first insulating layer and an edge portion of the first barrier layer exposed from an upper surface of the first insulating layer.
REFERENCES:
patent: 5391517 (1995-02-01), Gelatos et al.
patent: 5444022 (1995-08-01), Gardner
patent: 5510651 (1996-04-01), Maniar et al.
patent: 5571751 (1996-11-01), Chung
patent: 5614764 (1997-03-01), Baerg et al.
patent: 5666007 (1997-09-01), Chung
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5691572 (1997-11-01), Chung
patent: 5798299 (1998-08-01), Chung
patent: 5863835 (1999-01-01), Yoo et al.
patent: 5864179 (1999-01-01), Koyama
patent: 5889328 (1999-03-01), Joshi et al.
patent: 5939788 (1999-08-01), McTeer
patent: 5969422 (1999-10-01), Ting et al.
patent: 6008117 (1999-12-01), Hong et al.
patent: 6008118 (1999-12-01), Yeh et al.
patent: 6030896 (2000-02-01), Brown
patent: 6037250 (2000-03-01), Matsubara
patent: 6037278 (2000-03-01), Koyanagi et al.
patent: 6040627 (2000-03-01), Harada et al.
patent: 6077774 (2000-06-01), Hong et al.
Francos, P.L.L.C. Volentine
Oki Electric Industry Co. Ltd.
Peralta Ginette
LandOfFree
Semiconductor device having damascene interconnection... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having damascene interconnection..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having damascene interconnection... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3230756