Patent
1979-01-15
1981-07-14
Larkins, William D.
357 41, 357 71, H01L 2700
Patent
active
042789893
ABSTRACT:
A lower member of a cross wire structure formed in a semiconductor device, such as an MIS type semiconductor memory device, is provided with a structure of at least two layers of an impurity-containing polycrystalline semiconductor material according to the method disclosed. These layers are connected in parallel and their resistance is thus decreased. Furthermore, since these layers may be formed within insulating films over a semiconductor substrate, the degree of integration of the semiconductor device may be enhanced. The method for producing the cross electrodes allows simultaneous fabrication of other semiconductor devices, for instance MIS devices with components commonly fabricated with the cross electrode structures.
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patent: 4183040 (1980-01-01), Rideout
Baba Fumio
Miyasaka Kiyoshi
Mogi Jun-ichi
Yabu Takashi
Fujitsu Limited
Larkins William D.
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