Semiconductor device having contacting but electrically isolated

Details Semiconductor device having contacting but electrically isolated Semiconductor device having contacting but electrically isolated

1984-06-26

1985-10-15

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307475, 307584, 307280, 307304, 307300, H03L 100, H03L 500, H03K 1714, H03K 19003

Patent

active

045476810

ABSTRACT:
A semiconductor device includes p- and n-type semiconductor layers formed on an insulating substrate and gate electrodes selectively and insulatively formed over the respective p- and n-type semiconductor layers and forming D-type MOS transistors. In this semiconductor device, the p- and n-type semiconductor layers are made in contact with each other, and negative and positive power supply terminals which are respectively set at negative and positive potentials are respectively connected to the p- and n-type semiconductor layers thereby to electrically isolate the p-type and n-type semiconductor layers from each other.

REFERENCES:
patent: 3550097 (1970-12-01), Reed
patent: 3644905 (1972-02-01), Baker
patent: 4035829 (1977-07-01), Ipri et al.
patent: 4321489 (1982-03-01), Higuchi et al.
patent: 4408135 (1983-10-01), Yuyama et al.
patent: 4469962 (1984-09-01), Snyder
"Complementary Four Device FET Memory Cell", F. Gaensslen, IBM Technical Disclosure Bulletin, vol. 13, No. 12, May 1971, pp. 3614-3615.
"CMOS on Sapphire", Smith et al., Around the IC Loop, 8167 Computer Design, vol. 17, No. 9, pp. 194 and 196 (1978).

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