Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-02-23
2002-07-23
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S686000
Reexamination Certificate
active
06424049
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a chip-on-chip structure in which semiconductor chips are joined to each other by overlapping one of the semiconductor chips with the surface of the other semiconductor chip, and a semiconductor chip used therefor.
2. Description of Related Art
An example of a structure for miniaturizing and increasing the integration density of a semiconductor device is a so-called chip-on-chip structure in which paired semiconductor chips are overlapped with and joined to each other such that their surfaces are opposite to each other. In the chip-on-chip structure, a plurality of bumps are provided as a connecting portion on the surface of each of the semiconductor chips, and the bumps in the opposite semiconductor chips are joined to each other, to achieve electrical connection between the semiconductor chips.
The plurality of bumps can be formed in a state where they are raised from a surface protective film by selectively subjecting the surface protective film to plating using a material composing the bumps, for example. When the plurality of bumps are formed by the plating, however, the plurality of bumps formed on the surface protective film may, in some cases, vary in height depending on circumstances where the material composing the bumps is deposited.
In a case where the plurality of bumps in one of the semiconductor chips vary in height, when the semiconductor chip is joined to the other semiconductor chip, the low bump is not connected to the bump provided on the other semiconductor chip. Accordingly, electrical connection between the semiconductor chips may not be established in an area where the bumps are not connected to each other.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device having a chip-on-chip structure capable of reliably connecting semiconductor chips even if connecting portions in the semiconductor chips vary in height.
Another object of the present invention is to provide semiconductor chips for a semiconductor device of a chip-on-chip type capable of reliably connecting the semiconductor chips.
A semiconductor device according to the present invention comprises a first semiconductor chip having a connecting portion provided on its surface; a second semiconductor chip overlapped with and jointed to the surface of the first semiconductor chip and having a connecting portion provided on its surface opposite to the first semiconductor chip; and a deformable interlinkage for linking the connecting portion in the first semiconductor chip and the connecting portion in the second semiconductor chip together.
It is preferable that the connecting portions are respectively bumps formed in a raised state on the surfaces of the first semiconductor chip and the second semiconductor chip.
According to the present invention, even if the connecting portion in the first semiconductor chip and the connecting portion in the second semiconductor chip vary in height, the variation in the height can be absorbed by the deformation of the interlinkage when the first semiconductor chip and the second semiconductor chip are joined to each other. Consequently, it is possible to reliably connect the first semiconductor chip and the second semiconductor chip to each other.
It is preferable that the interlinkage comprises a connecting projection having flexibility provided in a standing condition on a vertex surface of the connecting portion in at least one of the first semiconductor chip and the second semiconductor chip.
According to the construction, when the first semiconductor chip and the second semiconductor chip are joined to each other, the connecting projection is deformed upon being brought into contact with the connecting portion in the opposite semiconductor chip, thereby making it possible to absorb the variation in the height of the connecting portions.
Furthermore, the interlinkage may comprise a flexible portion formed by giving flexibility to a vertex of the connecting portion in at least one of the first semiconductor chip and the second semiconductor chip.
According to the construction, when the first semiconductor chip and the second semiconductor chip are joined to each other, the flexible portion provided in the connecting portion in at least one of the semiconductor chips is deformed upon being brought into contact with the connecting portion in the other semiconductor chip, thereby making it possible to absorb the variation in height of the connecting portions.
The flexible portion may be a vertex of the connecting portion which is given flexibility by being formed in a tapered shape (an approximate cone or pyramid).
The interlinkage may comprise a recess formed on a vertex surface of the connecting portion in the first semiconductor chip or the second semiconductor chip.
According to the construction, the first semiconductor chip and the second semiconductor chip can be satisfactorily aligned with each other by inserting a front end of the connecting portion or the connecting projection into the recess to form a projection-dent coupling between the front end of the connecting portion or the connecting projection and the recess.
It is preferable that a low-melting metal having a lower melting point than that of a material composing the connecting portion is embedded in the recess. Consequently, it is possible to connect the front end of the connecting portion or the connecting projection which is inserted into the recess to the connecting portion having the recess formed therein through the low-melting metal in the recess. Consequently, it is possible to more reliably connect the first semiconductor chip and the second semiconductor chip to each other.
It is preferable that the interlinkage comprises a melting interlinkage which is provided in a standing condition on a vertex surface of at least one of the connecting portions in the first semiconductor chip and the second semiconductor chip and is composed of a low-melting metal having a lower melting point than that of a material composing the connecting portion.
According to the construction, when the first semiconductor chip and the second semiconductor chip are pressed against each other with the melting interlinkage abutted against the connecting portion, the connecting projection or the melting interlinkage in the opposite semiconductor chip while applying heat to their abutted portion, the melting interlinkage is melted and deformed by the heating. The connecting portion in the first semiconductor chip and the connecting portion in the second semiconductor chip are linked together by the deformed melting interlinkage. Even if the connecting portions vary in height, therefore, the variation in the height can be absorbed by the melting and the deformation of the melting interlinkage. Accordingly, the first semiconductor chip and the second semiconductor chip can be reliably connected to each other.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5818748 (1998-10-01), Bertin et al.
Potter Roy
Rader & Fishman & Grauer, PLLC
Rohm & Co., Ltd.
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