Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2002-12-10
2004-09-07
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S204000, C257S208000
Reexamination Certificate
active
06787823
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the configuration of a basic element aggregate to be incorporated into a large-scale semiconductor integrated circuit. More particularly, it relates to a cell-based basic element aggregate.
2. Description of the Background Art
Semi-custom LSIs are roughly classified into the following groups: PLD (programmable logic device), FPGA (field programmable gate array), gate array, and cell based IC (also referred to as a standard cell).
According to the gate array, primitive cells for constituting a gate are systematically arranged in advance on a semiconductor substrate. These cells are interconnected according to a user's circuitry, to realize a desired LSI.
FIG. 16
is a plan view illustrating gate array. In
FIG. 16
, gate interconnect lines
100
are shown to be equally spaced, namely, gate patterns (gate structures) are shown to be uniform according to the configuration of the gate array. An N-type impurity diffusion region, the gate interconnect line
100
, and another n-type impurity diffusion region adjacent to this gate interconnect line
100
form a transistor. These n-type impurity diffusion regions adjacent to each other through the gate interconnect line
100
are referred to as n-type active regions
101
. A plurality of p-type impurity diffusion regions arranged in the same manner as the plurality of n-type active regions
101
are referred to as p-type active regions
102
. The gate interconnect line
100
, the n-type active region
101
, and the p-type active region
102
are provided with contact holes
103
for interconnecting a plurality of transistors including the gate interconnect lines
100
, the n-type active regions
101
, and the p-type active regions
102
.
According to the cell based design, complex circuits such as a CPU, memory, A-D converter or micro cell are prepared in advance for forming a standard and basic element aggregate. These elements are selected and combined according to the function required by the user, to realize a desired LSI.
FIG. 17
is a plan view illustrating cell based design. In
FIG. 17
, gate patterns of gate interconnect lines
104
provided on active regions are shown to be nonuniform. As a result, space in one chip can be used more effectively than the gate array. An n-type impurity diffusion region, the gate interconnect line
104
, and another n-type impurity diffusion region adjacent to this gate interconnect line
104
form a transistor. These n-type impurity diffusion regions adjacent to each other through the gate interconnect line
104
are referred to as n-type active regions
105
. A plurality of p-type impurity diffusion regions arranged in the same manner as the plurality of n-type active regions
105
are referred to as p-type active regions
106
. The gate interconnect line
104
, the n-type active region
105
, and the p-type active region
106
are provided with contact holes
107
for interconnecting a plurality of transistors including the gate interconnect lines
104
, the n-type active regions
105
, and the p-type active regions
106
.
According to the foregoing cell based design, the gate interconnect lines
104
provided on the n-type active regions
105
or on the p-type active regions
106
may have nonuniformity in gate pattern (gate structure). In this case, complicated processing using CAD system is required in forming a mask, so that the gate interconnect lines
104
are uniform in finished gate pattern (gate structure). However, such complicated processing using CAD system causes the problem that huge amount of time and costs are required.
In order for the gate interconnect lines provided on the active regions to have uniform gate pattern (gate structure) while avoiding this problem, gate patterns (structures) thereof may be defined to be uniform in design stage. According to the cell based design in the background art shown in
FIG. 17
, however, uniformity of the gate patterns (gate structures) are not allowed according to whether the contact holes on the active regions are required or not. In order to realize uniform gate pattern (gate structure), the p-type active regions
106
can be defined to extend more widely as shown in
FIG. 18
, which in turn results in increase in area of the p-type active regions
106
and eventually, increase in area to be assigned exclusively to the basic element aggregate.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor integrated circuit having a basic element aggregate that realizes uniformity in finished gate pattern (gate structure) after wafer processing requiring no complicated processing using CAD system, while causing no increase in area to be assigned exclusively to the basic element aggregate.
According to the present invention, the semiconductor integrated circuit has a cell-based basic element aggregate. The cell-based basic element aggregate includes a first active region and a second active region provided on a semiconductor substrate, and a plurality of gate interconnect lines. The plurality of gate interconnect lines extend on the first and second active regions in a predetermined direction. The plurality of gate interconnect lines are equally spaced at least on the first and second active regions. At least one of the first and second active regions is provided with at least one protruding part extending in the predetermined direction. The cell-based basic element aggregate further includes a contact hole provided to the at least one protruding part.
At least one protruding part is provided to at least one of the first and second active regions. Therefore, uniformity of the gate interconnect lines in finished gate pattern (gate structure) is allowed on the first and second active regions after wafer processing requiring no complicated processing using CAD system. Further, there occurs no increase in area to be assigned exclusively to the basic element aggregate.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5164811 (1992-11-01), Tamura
patent: 5187556 (1993-02-01), Nariishi et al.
patent: 5598347 (1997-01-01), Iwasaki
patent: 5923060 (1999-07-01), Gheewala
patent: 2001-068653 (2001-03-01), None
Jackson Jerome
Renesas Technology Corp.
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