Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Signal transmission integrity or spurious noise override
Reexamination Certificate
1999-11-01
2001-07-31
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Signal transmission integrity or spurious noise override
C327S427000
Reexamination Certificate
active
06268757
ABSTRACT:
This patent application claims priority based on a Japanese patent application, H11-087769 filed on Mar. 30, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device which forms a capacity coupling between a power source voltage VDD and a power source voltage VSS by an FET provided inside a gate array.
2. Description of Related Art
FIG. 1
shows a conventional gate array GA. A plurality of gates is arranged all over the gate array GA shown in FIG.
1
(A). As shown in FIG.
1
(B), a basic cell BC is arranged at regular intervals covering the region where the gates are arranged. As shown in FIG.
1
(
c
), the basic cell usually has either four or eight FET. The desired circuit can be obtained by connecting the FET inside the basic cell BC by an aluminum wire.
FIG. 2
shows conventional inverters INV
10
and INV
12
, and also shows the current, which flows between the inverter INV
10
and the inverter INV
12
. The inverter INV
10
and the inverter INV
12
are formed by the FET inside the basic cell BC. A signal line LIN connects the inverter INV
10
and the inverter INV
12
. As shown in FIG.
2
(A), when the voltage Vout, which is a voltage output from inverter INV
10
, inverts from a Low signal to High signal, a power source current Ih flows from the power source voltage VDD to the signal line LIN. A wiring capacitance CL is generated in the signal line LIN, so that a part of the power source current Ih is consumed in charging the wiring capacitance CL. A pass-through current Ihl flows in the inverter INV
10
from the power source voltage VDD to the power source voltage VSS.
As shown in FIG.
2
(B), when the voltage Vout, which is a voltage output from the inverter INV
10
, inverts from a High signal to Low signal, a pass-through current Ihl flows in the inverter INV
10
from the power source voltage VDD to the power source voltage VSS. Because the electric charge, which is charged in the wiring capacitance CL, discharges, a power source current Il flows from the wiring capacitance CL to the power source voltage VSS of the inverter INV
10
.
FIG. 3
shows the waveform of the voltage input or output from the inverter INV
10
. FIG.
3
(A) shows the waveform of the voltage Vin, which is the voltage input to the inverter INV
10
.
FIG.
3
(B) shows the waveform of the voltage Vout, which is the voltage output from the inverter INV
10
. FIG.
3
(C) shows the waveform of the voltage VDD-VSS, which is the voltage obtained by subtracting the power source voltage VSS from the power source voltage VDD. As shown ain A of FIG.
3
(A), if the voltage Vin inverts from a Low signal to High signal, the voltage Vout inverts from a High signal to Low signal as shown in A of FIG.
3
(B).
When the electric charge, charged in the wiring capacitance CL of the signal line LIN, discharges, the power source current Il flows from the wiring capacitance CL to the power source voltage VSS of the inverter INV
10
. Because the electric charge, which is charged in the wiring capacitance CL, is discharged to the power source voltage VSS, the voltage VDD-VSS decreases for a moment as shown in A of FIG.
3
(C). Therefore, the decrease of the voltage Vout, which is output from the inverter INV
10
, is delayed.
Moreover, as shown in B of FIG.
3
(A), if the voltage Vin inverts from a High signal to Low signal, the voltage Vout inverts from a Low signal to High signal as shown in B of FIG.
3
(B). The power source current Ih flows from the power source voltage VDD of the inverter INV
10
to the signal line LIN. Because the wiring capacitance CL is generated in the signal line LIN, the power source current Ih is consumed for charging the wiring capacitance CL. The wiring capacitance CL consumes the power source current Ih, so the voltage VDD-VSS decreases for a moment as shown in B of FIG.
3
(C). Therefore, the increase of the voltage Vout delays as shown in FIG.
3
(B). The timing of which of the circuits inside a gate array operates lags by the fluctuation of the power source voltage VDD and VSS generated by the charging and discharging of the wiring capacitance CL. The result is, a decrease in the accuracy of the timing of the operation.
SUMMARY OF THE INVENTION
As stated, it is an object of the present invention to provide a semiconductor device that can solve the problems outlined above. The object of the present invention can be achieved by the combinations of features described in the independent claims of the present invention. The dependent claims define further advantageous embodiments of the present invention.
According to the first aspect of the present invention, a semiconductor device driven by two power source voltages VDD and VSS (VDD>VSS) can be provided. The semiconductor device comprises a base and a FET provided on the base. The FET has a gate, a source, a drain, and a substrate. The gate is connected to one of the two power source voltages VDD and VSS, and at least one of the source, the drain, or the substrate is connected to another one of the two power source voltages VDD and VSS. A capacity coupling is formed between the power source voltage VDD and the power source voltage VSS by a capacitance realized between the gate and at least one of the source, the drain, and the substrate.
A semiconductor device can be provided which further comprises a main power bus provided at least on the periphery of the semiconductor device. The main power bus provides the two power source voltages VDD and VSS to the FET. The FET is provided between the base and the main power bus, and a capacity coupling is formed by the FET between the power source voltage VDD and the power source voltage VSS of the main power bus.
A semiconductor device can be provided such that the FET is an N-type FET. The power source voltage VDD is applied to the drain and the source of the N-type FET, and the power source voltage VSS is applied to the gate and the substrate of the N-type FET.
A semiconductor device can be provided such that the FET is a P-type FET. The power source voltage VSS is applied to the drain and the source of the P-type FET, and the power source voltage VDD is applied to the gate and the substrate of the P-type FET.
A semiconductor device can be provided such that the FET is a N-type FET. The power source voltage VSS is applied to the drain, the source, and the substrate of the N-type FET, and the power source voltage VDD is applied to the gate of the N-type FET.
A semiconductor device can be provided such that the FET is a P-type FET. The power source voltage VDD is applied to the drain, the source, and the substrate of the P-type FET, and the power source voltage VSS is applied to the gate of the P-type FET.
A semiconductor device can be provided such that the FET is a N-type FET. The power source voltage VDD is applied to the drain, the source, and the gate of the N-type FET, and the power source voltage VSS is applied to the substrate of the N-type FET.
A semiconductor device can be provided such that the FET is a P-type FET. The power source voltage VSS is applied to the drain, the source, and the gate of the P-type FET, and the power source voltage VDD is applied to the substrate of the P-type FET.
A semiconductor device can be provided such that the FET is a P-type FET. The power source voltage VDD is applied to the gate of the P-type FET, and at least one of the drain and the source of the P-type FET is connected to the gate. Another one of the drain and the source is connected to the power source voltage VSS.
A semiconductor device can be provided such that the FET is a N-type FET. The power source voltage VSS is applied to the gate of the N-type FET, and at least one of the drain and the source of the N-type FET is connected to the gate. Another one of the drain and the source is connected to the power source voltage VDD.
A semiconductor device can be provided such that the FET is a P-type FET, and one of the powe
Advantest Corporation
Nu Ton My-Trang
Pillsbury & Winthrop LLP
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