Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-04-27
2002-05-14
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S511000, C257S622000, C257S640000, C438S424000, C438S434000, C438S436000, C438S435000, C438S431000
Reexamination Certificate
active
06388304
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a buried-type element isolation structure, and a method of manufacturing such a semiconductor device, and more specifically, to a semiconductor device in which elements are isolated by STI (shallow trench isolation) and a method of manufacturing such a device.
As is known, semiconductor devices having a buried-type element isolation structure entail the advantages of decreasing the size of element isolation regions, and achieving a well structure capable of suppressing the capacitance of the diffusion layer and being suitable for high-speed operation device.
For example, in order to maintain the capacitance of the diffusion layer at low, it suffices only if the concentration of impurities in the portion of the substrate, which corresponds to the bottom surface of the diffusion layer, or the concentration in the well is set to be sufficiently low. However, when the well concentration is lowered excessively, punching through between diffusion layers becomes uncontrollable. In order to avoid this, the concentration in the portion of the substrate, which corresponds to the bottom surface of the buried element isolation structure, or the well concentration is selectively increased, and thus the reduction of the capacitance of the diffusion layer and the control of the punch-through between diffusion layers are achieved at the same time in conventional techniques.
However, as the semiconductor devices are downsized, the trench for the element isolation becomes shallower (which is so-called STI). Therefore, even with the method described above, it is becoming difficult to achieve the reduction of the capacitance of the diffusion layer and the control of the punch-through for the element isolation, at the same time.
The conventional technique mentioned above will now be briefly reviewed with reference to
FIGS. 1A
to
1
D, which are cross sections illustrating a manufacturing step for manufacturing the conventional buried-type element isolation structure and drawback of such a conventional technique.
First, as shown in
FIG. 1A
, conventionally, a silicon oxide film
2
is formed to have a thickness of about 10 nm, on a semiconductor (silicon (Si)) substrate
1
by a thermal oxidation method or the like. Then, a silicon nitride film
3
is deposited to have a thickness of about 200 nm, on the silicon oxide film
2
by a chemical vapor growth method or the like. Further, thus resultant structure is treated in the following manner. That is, the silicon nitride film
3
, the silicon oxide film
2
and the silicon substrate
1
are subjected to anisotropic etching one after another by a photo-etching method. Thus, a buried type element isolation trench
4
having a predetermined shape is made. After that, heat oxidation is carried out, and consequently, a silicon oxide film
5
having a thickness of, for example, about 15 nm is formed on the inner wall of the buried element isolation trench
4
.
Next, as shown in
FIG. 1B
, for example, boron ions are implanted to the above-described structure at an acceleration voltage of 20 keV and a concentration of 1×10
13
cm
−2
in the case where the substrate (or well)
1
in the region where the buried element isolation trench
4
is formed is p-type. Or, for example, phosphor ions are implanted to the above-described structure at an acceleration voltage of 30 keV and a concentration of 1×10
13
cm
−2
in the case where the substrate (or well)
1
in the region where the buried element isolation trench
4
is formed is n-type. Thus, in a region of the substrate (or well)
1
, which corresponds to the bottom portion of the buried element isolation trench
4
, a punch-through suppression region
6
having the same conductivity type as that of the substrate (or well) of the region and having an impurity concentration higher than that of other substrate (or well)
1
located close thereto, is formed.
Further, to the structure shown in
FIG. 1B
, an insulating film
7
such as silicon oxide film is buried, and then the insulating film
7
is flattened by a CMP (chemical mechanical polish) method, or a resist etch back method or the like. Subsequently, the insulating film
7
, the silicon nitride film
3
and the silicon oxide film
2
are removed except for the matter inside the buried element isolation trench
4
, thus completing a buried type element isolation structure
7
′ as shown in FIG.
1
C.
Next, as shown in
FIG. 1C
, for example, arsenic ions are implanted to the above-described structure at an acceleration voltage of 40 keV and a concentration of 3×10
15
cm
−2
in the case where the substrate (or well)
1
in the region where the element isolation structure
7
′ is formed is p-type. Or, for example, BF
2
ions are implanted to the above-described structure at an acceleration voltage of 30 keV and a concentration of 3×10
15
cm
−2
in the case where the substrate (or well)
1
in the region where the element isolation structure
7
′ is formed is n-type. Thus, a high-concentration diffusion layer region
8
is formed in a vicinity of the surface portion of the substrate (or well)
1
.
After that, as shown in
FIG. 1D
, an interlayer insulating film
10
is deposited on the high-concentration diffusion layer region
8
and the element isolation structure
7
′, and a contact
11
designed to make an electrical contact with the high-concentration diffusion layer region
8
is formed in the interlayer insulating film
10
. Further, a metal wiring
12
which is connected to the contact
11
is formed on the interlayer insulating film
10
.
However, the element isolation structure
7
′ thus formed entails the following drawbacks.
That is, it is originally preferable that the high-concentration diffusion layer region
8
shown in
FIG. 1C
should be in contact with a substrate (or well)
1
of a lowest possible concentration, in order to keep the capacitance of the bottom surface at low. However, in the manufacturing step described above, the high-concentration diffusion layer region
8
and the punch-through suppression region
6
are brought into contact with each other in a region
9
located close to the element isolation structure
7
′. Therefore, in the close region
9
, the reduction of the capacitance cannot be realized, which is not preferable to increase the high-speed operation of the semiconductor device.
Further, as counter-measurements, there is a method of implanting ion only to the substrate (or well)
1
, which corresponds to the bottom portion of the element isolation structure
7
′, in order to suppress the punch-through. However, even in the method, impurities diffuse in the substrate (or well)
1
in the lateral direction. For this reason, in devices of the future, which have shallower element isolation structure
7
′, it becomes difficult to reduce the capacitance of the diffusion layer.
More specifically, as the semiconductor device is downsized, the possibility where the punch-through suppression region
6
and the high-concentration diffusion layer region
8
are in contact with each other becomes higher. This is because although the high-concentration diffusion layer region
8
becomes thinner, the size of the punch-through suppression region
6
is not always reduced, in order to maintain the concentration of the impurities in the punch-through suppression region
6
, which accords with the downsizing. Therefore, the high-concentration diffusion layer region
8
and the high-concentration punch-through suppression region
6
can be easily brought in contact with each other, and it becomes further difficult to form a low-capacitance diffusion layer.
Further, as can be seen in
FIG. 1D
, as the downsizing proceeds, the distance between the contact
11
used to obtain electrical contact with the high-concentration diffusion layer region
8
, and the element isolation structure
7
′ becomes shorter. Therefore, when a mask alignment er
Kasai Kunihiro
Matsuoka Fumitomo
Everhart Caridad
Kabushiki Kaisha Toshiba
Yevsikov V.
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