Patent
1978-10-18
1981-01-06
Wojciechowicz, Edward J.
357 69, 357 71, H01L 2348
Patent
active
042440025
ABSTRACT:
A semiconductor structure in which metallic connecting leads are bonded to bump terminal electrodes by thermal pressure bonding. A stress mitigation layer is advantageously provided in the semiconductor structure which prevents or reduces breaking of the semiconductor substrate or an insulating film when thermal pressure bonding is applied to the bump terminal electrode.
REFERENCES:
patent: 4051508 (1977-09-01), Sato et al.
patent: 4060828 (1977-11-01), Satonaka
Sato Susumu
Tsunemitsu Hideo
Nippon Electric Co. Ltd.
Wojciechowicz Edward J.
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