Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-03-21
2003-04-22
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S107000, C438S108000, C438S051000, C438S065000, C438S121000, C257S678000, C257S685000, C257S686000
Reexamination Certificate
active
06551854
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 USC § 119 to Japanese Patent Application No. 2000 -88452, filed on Mar. 28, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device in which a bump electrode is used for electric and mechanical connections between electrodes, and a method of manufacturing such a semiconductor device. Further, the invention relates to a semiconductor device in which an electrode on a substrate and a bonding pad of a semiconductor element (or a semiconductor chip) are electrically and mechanically connected via a bump electrode, and a method of manufacturing such a semiconductor device.
2. Description of the Related Art
Semiconductor devices applied to a portable terminal equipment such as a lap-top personal computer, a portable phone or the like are required to be very compact and light in weight in order to make the foregoing equipment more portable. Such semiconductor devices should have excellent electrical performance in order to assure high speed operation. In order to meet these requirements, semiconductor devices tend to employ a flip-chip structure.
The flip-chip structure features that an electrode of a substrate and a bonding pad of a semiconductor element are electrically and mechanically connected via a bump electrode. Fundamentally, the plane size of the substrate can be made as small as the plane size of the semiconductor element, which enables the semiconductor device of the flip-chip structure to be compact and light in weight. Further, no long bonding wire is used between the electrode of the substrate and the bonding pad of the semiconductor element, so that the semiconductor device can raise its operation frequency. In short, the flip-chip structure can accelerate the operation of the semiconductor device.
The semiconductor devices with the flip-chip structure are mainly classified into those which adopt a contact connection between the electrodes, and those which adopt an alloy connection between the electrodes.
In the former case, a flip-chip connection is performed using an anisotropic conductive film (ACF). The anisotropic conductive film is placed between an electrode of a substrate and a bonding pad of a semiconductor element, and mechanically connects them through thermo-compression. However, since not only a contact resistance between the anisotropic conductive film and the electrode but also a contact resistance between the anisotropic film and the bonding pad are so large that this type of connection cannot be applied to a semiconductor device which has to operate quickly.
In the latter case, an alloy layer is formed between the electrode of the substrate and the bump electrode in order to connect the electrodes. This alloy connection method can reduce the contact resistance between the electrode and the bump electrode, which enables the semiconductor device to operate at a high speed.
Referring to FIG.
8
and
FIG. 9
of the accompanying drawings, a semiconductor device
100
of the flip-chip structure in the alloy connection method comprises electrodes
102
on a substrate
101
, low-melting metal layers
121
on the electrodes
102
, bump electrodes
123
on the metal layers
121
, and bonding pads
111
for a semiconductor element
110
on the metal layers
121
, and also includes alloy layers
122
between the low-melting metal layers
121
and the bump electrodes
123
.
The electrode
102
is made of Cu foil, and the bonding pad
111
is made of an Al alloy film. The bump electrode
123
is made of Au, and the low melting metal layer
121
is made of an Sn—Ag alloy. The alloy layer
122
is made of an Au—Sn eutectic alloy (i.e. 80 weight percents of Au and 20 weight percents of Sn). The Sn—Ag eutectic alloy is made of Sn of the low-melting metal layer
121
and Au of the bump electrode
123
.
When the alloy layer
122
is made of the Au—Sn eutectic alloy in the semiconductor device
100
, Cu of the electrode
102
of the substrate
101
is diffused into the Au—Sn eutectic alloy, and a part of the alloy layer
122
changes to a ternary Au—Sn—Cu alloy. Simultaneously, Au and Sn of the Au—Sn eutectic alloy diffuse into the electrode
102
. However, Cu quickly diffuses into the Au—Sn eutectic alloy compared with Au and Sn which diffuse into the electrode
102
. It is therefore known that voids are caused between Cu and the Au—Sn—Cu alloy because of the Kirkendall effect. (For instance, refer to Au—Sn Bonding Metallurgy of TAB contacts and its influence on the Kirkendall effect in ternary Cu Au—Sn system. 1992 Proceedings. 42nd Electronic Components and Technology Conference (Cat. No. 92CH3056-9) (USA) xviii+1095 P.P.360-71, and so on.) It has been pointed out that the voids may deteriorate mechanical contact strength of the alloy layer
122
and disconnection due to a heat cycle.
In the foregoing semiconductor device
100
, the alloy layer
122
is made of the Au—Sn eutectic alloy, so that the volume of the low-melting metal layer
121
is approximately 1.5 to 2 times larger than that of the bump electrode
123
. If the low-melting metal layer
121
excessively supplies Sn, intermetallic compounds such as stable Au—Sn, Au—Sn
2
, Au—Sn
4
or the like are produced, and these intermetallic compounds are very weak. In other words, they tend to reduce the mechanical contact strength of the alloy layer
122
and cause disconnection due to the heat cycle.
SUMMARY OF THE INVENTION
According to the invention, a semiconductor device comprising: a first electrode; a bump electrode formed on the first electrode and mainly made of Au; a second electrode formed on the bump electrode; and a bonding layer provided between the first electrode and the bump electrode and mainly made of an intermetallic compound which consist of Au of the bump electrode and a low-melting metal.
Further, according to the invention, a method of manufacturing a semiconductor device, comprising the steps of (1) forming a low-melting metal layer on a first electrode; (2) forming a bump electrode on a second electrode, the bump electrode being mainly made of at least Au; (3) and bringing the low-melting metal layer into contact with the bump electrode, heating these components, and forming a bonding layer mainly made of intermetallic compounds which consist of Au of the bump electrode and low melting metals.
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E. Hosomi et al., “A New Bonding M echanism of 50 &mgr;m Pitch TAB-ILB with 0.25 &mgr;m Sn Plated Cu Lead”,Proceedings of ECTC '95, pp. 851-856, (1995).
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Hosomi Eiichi
Koshio Yasuhiro
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Lee Jr. Granvill D
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