Fishing – trapping – and vermin destroying
Patent
1994-10-24
1996-01-02
Limanek, Robert P.
Fishing, trapping, and vermin destroying
437133, 437107, H01L 21205
Patent
active
054808332
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention generally relates to semiconductor devices and more particularly to the fabrication of a compound semiconductor device that includes a layer of group III-V compound semiconductor material.
In the integrated circuit of semiconductor devices, it is essential to achieve a device isolation between adjacent devices. In the silicon devices, such an isolation can be achieved relatively easily by forming a film of silicon oxide. In the integrated circuit of semiconductor devices that use the group III-V compound semiconductor material for the essential part of the device, the device isolation raises a problem as the formation of the device isolation region by the oxidation process is generally not possible in such a device.
In order to achieve the effective device isolation in the group III-V semiconductor devices, it has been practiced to incorporate the so-called deep impurity elements into the semiconductor layer. When such deep impurity elements are incorporated, a pinning of the Fermi level occurs generally at the center of the forbidden band and the semiconductor material shows an increased resistivity.
Conventionally, the foregoing incorporation of the deep impurity elements has been achieved by using the ion implantation technique. In this technique, the elements such as Oxygen or chromium are introduced into the semiconductor layer in correspondence to the region located between adjacent devices to form an isolation region that extends from the surface of the device toward the substrate.
BACKGROUND ART
FIG. 1 shows an example of the conventional device that employs such a device isolation.
Referring to FIG. 1, the device is a typical HEMT and includes a channel layer 3 of undoped GaAs and an electron supplying layer 5 of n-type AlGaAs that is provided on the channel layer 3 with an undoped spacer layer of AlGaAs interposed therebetween. Further, a cap layer 6 of n-type GaAs is provided on the electron supplying layer 5, and another cap layer 7 that contains layers of n-type AlGaAs and n-type GaAs is provided further on the cap layer 7. On the cap layer 7, a number of gate electrodes 8A, 8B, . . . are provided in correspondence to a number of devices formed on the substrate.
In order to isolate the individual devices, the device of FIG. 1 uses an isolation region 9 that is formed in correspondence to the boundary between adjacent devices such that the region 9 extends from the surface of the layer 9 toward the substrate 1, passing through the layers 3-7. Typically, the region 9 is formed by incorporating oxygen or chromium ions by an ion implantation process and has an increased resistivity due to the foregoing pinning of the Fermi level. Thereby, the passage of the carriers from one device to another device is prevented.
Further, the foregoing layers 3-7 forming the active part of the device are formed on a semi-insulating GaAs substrate 1 that is covered with a buffer layer 2 such that the buffer layer 2 isolates the active part of the device from various adversary surface states or defects that are formed on the surface of the substrate 1. Typically, the buffer layer 2 is formed of an undoped AlGaAs and has a large resistivity. Thereby, each device is laterally isolated by the device isolation region 9 and vertically by the buffer layer 2, and the penetration of the carriers from one device to an adjacent device is prevented.
In such a conventional isolation structure, there exists a problem in that, although the penetration of the carriers from one device to the adjacent device can be minimized, the shielding of the electric field between the devices cannot be achieved successfully. It should be noted that the high purity buffer layer 2 lacks electric charges therein and passes the line of electric force and hence the electric field freely. Thereby, the electric field of one device penetrates into the region of the adjacent device and the operational characteristic of the device such as the threshold voltage tends to be influenced by the state of the adjacent d
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Kikkawa Toshihide
Ohori Tatsuya
Fujitsu Limited
Hardy David B.
Limanek Robert P.
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