Semiconductor device having an internal voltage generating...

Details Semiconductor device having an internal voltage generating... Semiconductor device having an internal voltage generating...

1999-02-26

2001-10-02

Han, Jessica (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S314000, C365S226000

Reexamination Certificate

active

06297624

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a structure of an internal voltage generating circuit for internally generating a voltage at a desired level.
2. Description of the Background Art
FIG. 47
schematically shows a whole structure of a conventional semiconductor memory device. In
FIG. 47
, the semiconductor memory device includes a memory cell array
100
having a plurality of memory cells MC arranged in rows and columns. In memory cell array
100
, word lines WL are arranged corresponding to the rows of memory cells MC, respectively, and bit line pairs BLP are arranged corresponding to the columns of memory cells MC, respectively. Memory cells MC are arranged corresponding to crossings between bit line pairs BLP and word lines WL, respectively.
The semiconductor memory device further includes an address input buffer
200
which takes in an externally supplied address signal ADD to produce an internal address signal, a row select circuit
250
which drives a word line WL corresponding to an addressed row in memory cell array
100
to the selected state in accordance with an internal row address signal from address input buffer
200
, a sense amplifier circuit
300
which senses, amplifies and latches data of the memory cells connected to the selected row, a column select circuit
350
which selects an addressed column in memory cell array
100
in accordance with an internal column address signal from address input buffer
200
, and an I/O circuit
400
which transmits data to and from the memory cell in the column selected by column select circuit
350
.
Row select circuit
250
includes a row decoder for decoding the internal row address signal from address input buffer
200
, and a word line drive circuit for driving the word line by the output signal of the row decoder to the selected state. The column select circuit
350
includes a column decoder for decoding the internal column address signal from address input buffer
200
, and an I/O gate circuit for connecting the addressed column in the memory cell array to an internal data bus (not clearly shown) in accordance with a column select signal from the column decoder. Sense amplifier circuit
300
includes sense amplifiers which are provided corresponding to bit line pairs BLP, and differentially amplify potentials on the corresponding bit line pairs when made active, respectively.
Semiconductor memory device further includes an internal power supply circuit
500
which down-converts an externally supplied power supply voltage Vext to produce internal power supply voltages Vccp and Vccs. Internal power supply voltage Vccp produced by internal power supply circuit
500
is supplied to peripheral circuits, i.e., address input circuit
200
, row select circuit
250
, column select circuit
350
and I/O circuit
400
. Internal power supply voltage Vccs is supplied to sense amplifier circuit
300
.
Internal power supply voltage Vccp is at a level higher than or equal to that of internal power supply voltage Vccs. By applying high internal power supply voltage Vccp to the peripheral circuits, the peripheral circuits are operated fast. Meanwhile, by applying internal power supply voltage Vccs lower than internal power supply voltage Vccp to sense amplifier circuit
300
, a charge/discharge current of the bit line is reduced and the bit line signal amplitude is also reduced, whereby a fast access operation is achieved. If the device is a DRAM (Dynamic Random Access Memory), memory cell MC is formed of an access transistor and a capacitor. In this case, application of a high voltage to an insulating film of this capacitor is prevented so that the reliability of capacitor insulating film can be assured. Further, it is possible to ensure a reliability of the word lines subjected to a 1.5 times higher voltage than voltage Vccs.
In address input buffer
200
and I/O circuit
400
, external power supply voltage Vext is used for portions interfaced to an external device, although not shown in FIG.
47
.
As a storage capacity of the semiconductor memory device increases, MOS transistors as the components are miniaturized accordingly. However, external devices such as a processor and a logic have not been highly miniaturized compared with the semiconductor memory devices, and therefore relatively high operation power supply voltages are used for maintaining intended operation speeds. It is necessary to maintain compatibility in the power supply voltage with previous-generation semiconductor memory devices. Accordingly, external power supply voltage Vext is lowered by internal power supply circuit
500
to produce internal power supply voltages Vccp and Vccs so that the compatibility of the system power supply voltage is maintained while maintaining the compatibility with previous-generation semiconductor memory devices.
FIG. 48
schematically shows a structure of internal power supply circuit
500
shown in FIG.
47
. In
FIG. 48
, internal power supply circuit
500
includes a reference voltage generating circuit
502
s
generating a reference voltage Vrefs, a reference voltage generating circuit
502
p
generating a reference voltage Vrefp, a voltage down converter
504
s
which is supplied with a current from a node receiving external power supply voltage Vext and adjusting a voltage level of internal (sense) power supply voltage Vccs in accordance with a difference between internal power supply voltage Vccs and reference voltage Vrefs, and a voltage down converter
504
p
which is supplied with a current from a node receiving external power supply voltage Vext and adjusting a voltage level of internal power supply voltage Vccp in accordance with a difference between internal power supply voltage Vccp and reference voltage Vrefp. Reference voltage generating circuit
502
s
and voltage down converter
504
s
form a sense power supply circuit producing an internal power supply voltage for the sense amplifiers. Reference voltage generating circuit
502
p
and voltage down converter
504
p
form a peripheral power supply circuit producing internal power supply voltage Vccp for the peripheral circuits. The sense power supply circuit and the peripheral power supply circuit are made independent from each other for the following reasons.
During an operation of sense amplifier circuit
300
shown in
FIG. 47
, bit line pairs BLP connected to a selected word line WL are charged and discharged. The charge/discharge current during the operation of the sense amplifiers is relatively large, and voltage down converter
504
s
of the sense power supply circuit is required to have a large current drive capability for compensating for this large current consumption. However, only the charging and discharging of the bit line pair BLP are required, and fast recovering of internal power supply voltage (which will be referred to as a “sense power supply voltage”) Vccs to the initial state is not required. Therefore, a significantly fast responsibility is not required in voltage down converter
504
s
. In contrast, a sufficiently fast responsibility is required in voltage down converter
504
p
of the peripheral power supply circuit because fast compensation must be made for a variation in internal power supply voltage (which will be referred to as a “peripheral power supply voltage”) Vccp so as to achieve fast and stable operation of the peripheral circuits. Meanwhile, the peripheral circuits in operation consume a current smaller than that in the operation of the sense amplifier. Accordingly, voltage down converter
504
p
of the peripheral power supply circuit is required to have a fast responsibility although the required drive current is relatively small. For satisfying these different required characteristics, the sense power supply circuit and the peripheral power supply circuit are arranged independently of each other.
The semiconductor memory device includes the independent power supply circuits for the peripheral circuit and for the sense amplifier cir

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