Semiconductor device having an interconnect layer with a...

Details Semiconductor device having an interconnect layer with a... Semiconductor device having an interconnect layer with a...

2002-05-16

2004-01-27

Williams, Alexander O. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S775000, C257S758000, C257S700000, C257S701000, C257S208000, C257S760000

Reexamination Certificate

active

06683382

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit manufacturing, and, more particularly, to dummy fill features in an interconnect layer.
BACKGROUND OF THE INVENTION
Chemical-mechanical polishing (CMP) is a technique for planarizing an interconnect layer overlying a semiconductor substrate. Typically, multiple interconnect layers are stacked over the semiconductor substrate, wherein each interconnect layer includes active interconnect features connecting active areas of the semiconductor substrate. An active area is that portion of the semiconductor substrate in which components are built, such as transistors, capacitors and resistors.
It is desirable to have a flat or planarized upper surface of each interconnect layer prior to forming subsequent interconnect layers. Depending on the density of the area occupied by the active interconnect features, the upper surface may not always be flat after deposition of a dielectric material, thus the need for CMP.
The active interconnect features in an interconnect layer are separated by trenches. Referring to
FIG. 1.
, the trenches
10
and
12
between active interconnect features
20
,
22
and
24
are much narrower than the trench
14
between active interconnect features
24
and
26
. One approach for filling the trenches
10
,
12
and
14
with dielectric material, particularly when the trenches are between closely spaced active interconnect features, is by a high density plasma chemical vapor deposition (HDP-CVD) process. If the deposited dielectric material
34
has a sufficient thickness, then the single step deposition process allows the interconnect layer
30
to be planarized.
As a result of the HDP-CVD process, there are protrusions
32
in the upper surface of the dielectric material
34
above respective active interconnect features
20
-
26
. Each protrusion
32
has associated therewith a bias. This bias can be defined as either positive or negative. For the HDP-CVD process as illustrated in
FIG. 1
, each protrusion
32
has a negative bias, i.e., the width of the protrusion is less than the width or lateral dimension
90
of the underlying active interconnect feature. Where there are no active interconnect features, such as between active interconnect features
24
and
26
, the upper surface of the dielectric material
34
is relatively flat.
Another approach for depositing the dielectric material is by a two-step process, as shown in FIG.
2
. The first step is the HDP-CVD process for filling in the trenches
10
-
14
with the dielectric material
34
between the active interconnect features
20
-
26
. Once the trenches
10
-
14
are filled, a plasma enhanced chemical vapor deposition (PE-CVD) process adds additional dielectric material
35
allowing a combined thickness sufficient for planarization. The protrusions
42
formed above the respective active interconnect features
20
-
26
after the PE-CVD process results in a positive bias. Positive bias is where the width of the protrusion
42
is greater than the width or lateral dimension
90
of the underlying active interconnect feature.
Depending on the deposition process, CMP is used to eliminate the protrusions
42
having positive bias and the protrusions
32
having a negative bias. However, if pattern density variations of the active interconnect features
20
-
26
are large, CMP is not adequate to sufficiently planarize the interconnect layer
30
. For example, planarization of the relatively flat dielectric material overlying active interconnect features
24
and
26
results in over polishing. This causes significant dishing in the dielectric material
34
or
35
, which results in a non-planarized surface. A non-planarized surface of the interconnect layer
30
may cause reliability problems with an overlying interconnect layer.
One approach for preventing over polishing is to place dummy fill features in the open regions adjacent active interconnect features for preventing pattern density variations of the active interconnect features. Placement of the dummy fill features is typically done using a layout algorithm as part of a layout editor or an automated pattern generator.
Conventional layout algorithms for placing dummy fill features in open areas of the interconnect layer are performed based upon a predetermined set density. Each open area to be filled with dummy fill features will have the same density. In other words, the dummy fill feature density is independent of the density of the adjacent active interconnect features. An open area is defined as any area within the interconnect layer that does not have metal therein. The fill feature density is defined as the ratio of the area occupied by the metal to the total area.
However, if the density of an active interconnect feature is high with respect to an adjacent open area, it is not always necessary to place dummy fill features in the corresponding open area at the same predetermined set density. Unnecessarily placing dummy fill features adds to the parasitic capacitance of the interconnect layer. Moreover, there is no constant overall fill density between open areas of the interconnect layer. This variation in the density of the interconnect layer also causes deviations when the interconnect layer is planarized. Therefore, there is a need for making a layout for an interconnect layer that determines placement of dummy fill features for achieving a uniform density throughout the interconnect layer.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for making a layout for an interconnect layer that has uniform density throughout to facilitate planarization during manufacturing of a semiconductor device.
Another object of the present invention is to position dummy fill features within the interconnect layer to minimize parasitic capacitance with adjacent interconnect features.
These and other objects, advantages and features in accordance with the present invention are provided by a method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device, wherein the method comprises the steps of determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout, and adding dummy fill features to each layout region to obtain a desired density of active interconnect features and dummy fill features to facilitate uniformity of planarization during manufacturing of the semiconductor device.
An important feature of the present invention is that each layout region preferably has a uniform density. By adding dummy fill features to obtain a desired density of active interconnect features and dummy fill features, dummy fill features are not unnecessarily added. Unnecessarily adding dummy fill features would undesirably increase the parasitic capacitance of the interconnect layer.
When each layout region has a uniform density, the dummy fill features thus facilitate uniformity of planarization during manufacturing of the semiconductor device. Another important feature of the present invention is that positioning of the dummy fill features is preferably based upon capacitance with adjacent active interconnect features. Likewise, the dummy fill features are also preferably positioned based upon capacitance with adjacent active interconnect features in an adjacent interconnect layer.
Yet another important feature of the method of the present invention preferably includes defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias for a dielectric layer to be deposited over the interconnect layer. After a single step HDP-CVD process, the protrusion in the dielectric material overlying a respective active interconnect feature has a negative bias. Negative bias is where the width of the protrusion is less than the width or lateral dimension of the underlying active interconnect feature. In one embodiment, the lateral dimension of the dummy fill featur

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