Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-10-21
2002-02-12
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C710S063000, C710S063000
Reexamination Certificate
active
06346482
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, such as an IC or an LSI, as well as to a method of manufacturing the semiconductor device. Particularly, the present invention relates to a semiconductor device and a manufacturing method thereof in which contact holes are formed in a self-aligned manner.
The present invention relates to a semiconductor device, such as an IC or an LSI, as well as to a method of manufacturing the semiconductor device. Particularly, the present invention relates to a semiconductor device and a manufacturing method thereof in which contact holes are formed in a self-aligned manner.
2. Background Art
In recent years, a self-aligned contact hole (SAC), such as that shown in
FIG. 34
, has been adopted, as the development of a semiconductor device has advanced toward higher integration and further improved performance, as exemplified by the recently-developed ULSI.
In order to form a self-aligned contact hole, on a silicon semiconductor substrate
1
, an element isolation region
2
is first formed as shown in FIG.
34
. Subsequently, a gate oxide film
3
, a gate electrode
4
, and a protective oxide film
5
are formed into predetermined patterns on the substrate
1
. A thin protective film
7
is deposited so as to provide electrical isolation on the overall construction of the gate electrode
4
. An etching stopper film
8
made of a silicon nitride film is deposited on the oxide film
7
, and an interlayer oxide film
11
is deposited on the etching stopper film
8
. After a pattern has been formed by means of a photoresist
12
, a contact hole
15
is formed by etching.
At this time, the etching of the interlayer oxide film
11
must be stopped at the silicon nitride film
8
. If the etching operation is not stopped, the gate electrode
4
will become exposed as shown in
FIG. 35
, resulting in short-circuiting with an upper wiring layer. To prevent the short-circuit, there must be ensured sufficient etch selectivity between the interlayer oxide film
11
and the silicon nitride film
8
.
Further, under such a conventional method, a hole is opened with high etch selectivity with respect to the etching stopper film
8
, and in a subsequent step, the etching stopper film is removed from the bottom of the hole. Thus, formation of a hole involves two manufacturing steps, adding to cost and resulting in lower-yield manufacture.
Further, as wiring pitches are miniaturized, the aspect ratio of the hole to be etched increases. Then, as show in
FIG. 36
, when an opened contact hole is filled with wiring material
21
, a void (gap) becomes more apt to arise in an area sandwiched between the gate electrodes at the bottom of the contact hole.
To form a contact hole by means of the self-alignment method, the interlayer oxide film
11
is etched, and a flat portion of the nitride film
8
serving as an etching stopper film is also removed. On the other hand, a tapered area of the etching stopper film provided in the bottom of the contact hole or the etching stopper film provided in proximity of the gate electrodes is desirably left substantially intact in order to protect the gate electrodes.
Therefore, the etching rate at the tapered area of the etching stopper film is desirably lower than that of the interlayer oxide film, according to a difference in material between the nitride film and the interlayer oxide film. That is, the etching selectivity between a nitride film and a interlayer oxide film is desirably large.
A mixture of C
4
F
8
gas and CH
2
F
2
gas such as those described in, e.g., Japanese Patent Application Laid-open No. Hei-7-161702 is used for etching a contact hole. In such a dry etching operation, a tapered portion of an etching stopper film is more likely to be etched through sputtering of ions than is a plane portion of the same. For this reason, when a etching stopper film is thin or etching selectivity is insufficient for a tapered portion, the etching stopper film provided at the tapered area is removed simultaneously with the etching of the interlayer oxide film, depending on a positional relationship between the resist pattern and the gate electrode. Resultantly, a dielectric film surrounding the gate electrode is rendered thin. If a contact hole is formed in this situation, a voltage withstand failure may be caused between the gate electrode and a wiring layer to be subsequently formed, thus resulting in a short-circuit and an operation failure.
A conceivable measure to prevent these failures is to increase the thickness of the etching stopper film
8
shown in
FIG. 34
, to increase the thickness of an oxide film side wall (not shown), as well as to increase the thickness of the protective oxide film
5
. Although this method enables prevention of a short-circuit between the gate electrode
4
and a wiring layer to be subsequently formed, the surface irregularities become significant, thus imposing a problem on a subsequent manufacturing process.
FIGS. 37 and 38
show an example of a step of forming a bit line contact (BC) hole during the process of manufacturing a conventional semiconductor memory.
FIG. 38
is aplan view, and
FIG. 37
is across-sectional view taken along a broken line provided in FIG.
38
. In
FIGS. 37 and 38
, reference numeral
1
designates a semiconductor substrate (Si);
4
designates a gate wiring pattern including gate electrodes;
8
designates a nitride film used for forming a BC hole in a self-aligned manner; and
11
designates an interlayer oxide film.
According to the existing technique, after formation of the interlayer oxide film
11
, the photoresist
12
is patterned, thus opening the contact hole
15
(i.e., a bit line contact). At this time, the contact hole
15
is usually formed into a square pattern or a nearly-square pattern. When the interlayer oxide film
11
is etched up to the nitride film
8
, the contact hole
15
designed according to such standards is apt to reach the shoulder portion of the nitride film
8
.
Deposited components are less likely to adhere to the shoulder portion of the nitride film
8
, and hence the shoulder portion of the nitride film
8
is apt to be removed, thus resulting in high possibility of short-circuit between wiring patterns such as that shown in FIG.
39
.
Further, the interlayer insulating film
11
and the silicon nitride film
8
have similar characteristics and are etched by the same etching gas, so that it is difficult to secure sufficient etching selectivity between the two films. Therefore, it is required to adopt an etching stopper film that shows an sufficient etching selectivity.
The present invention has been conceived to solve the foregoing problems, and the object of the present invention is to provide a semiconductor device which has a structure to prevent deterioration of the electric characteristics of the device when a contact hole is formed by a self-alignment method, by preventing etching of an electrode protecting area. Further object of the present invention is to provide a method of manufacturing a semiconductor device which enables improvement in reliability of the device and which enables improved-yield in manufacture of the device.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, in a method of manufacturing a semiconductor device, a resist mask is formed on a silicon oxide film laid on a silicon nitride film having a step portion on a semiconductor substrate, in such a way as to have an opening above said step portion. Then, the silicon oxide film is etched through said opening of the resist mask, by means of plasma etching through use of a processing gas comprising a mixture of a rare gas and a CF-based gas, thereby tapering the shoulder of said step portion of said silicon nitride film.
In another aspect, in the method, a mix ratio of said rare gas and said CF-based gas is adjusted to control the position where the step portion of the the silicon nitride film is tapered.
According to another aspect of the present invention, in a metho
Fukao Tetsuhiro
Kusumi Yoshihiro
Matsumoto Junko
Ohmi Kazuyuki
Sakamori Shigenori
Kunemund Robert
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Umez-Eronini Lynette T.
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