Semiconductor device having an element with circuit pattern ther

Details Semiconductor device having an element with circuit pattern ther Semiconductor device having an element with circuit pattern ther

1996-03-22

1998-11-10

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

257737, 257738, 257723, 257700, 257781, 257758, H01L 2310, H01L 2302, H01L 2348, H01L 2940

Patent

active

058348441

ABSTRACT:
A process for making a chip sized semiconductor device, in which a semiconductor chip is prepared so as to have electrodes on one of surfaces thereof and an electrically insulating passivation film formed on the one surface except for areas where the electrodes exist. An insulation sheet is prepared so as to have first and second surfaces and a metallic film coated on the first surface. The second surface of the insulation sheet is adhered on the one surface of the semiconductor chip. First via-holes are provided in the metallic film at positions corresponding to the electrodes. Second via-holes are provided in the insulation sheet at positions corresponding to the first via-holes so that the electrodes are exposed. The metallic film is electrically connected to the electrodes of the semiconductor chip through the first and second via-holes. A circuit pattern is formed from the metallic film so that the circuit pattern has external terminal connecting portions. An insulation film is adhered on the insulation sheet so that the external terminal connecting portions are exposed. External connecting terminals are electrically connected to the external terminal connecting portions of the circuit pattern.

REFERENCES:
patent: 4907039 (1990-03-01), Chikaki
patent: 5034345 (1991-07-01), Shirahata
patent: 5046161 (1991-09-01), Takada
patent: 5394013 (1995-02-01), Oku et al.
patent: 5604379 (1997-02-01), Mori
patent: 5631499 (1997-05-01), Hosomi et al.
patent: 5656863 (1997-08-01), Yasunaga et al.
patent: 5677576 (1997-10-01), Akegawa

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