Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2002-12-02
2004-04-13
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C438S689000
Reexamination Certificate
active
06720667
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device, such as a high voltage device used in a liquid crystal display (LCD) driving integrated circuit, having an align key used for precise alignment when defining an active region on a semiconductor substrate having a well, and a method for manufacturing the same.
2. Description of the Related Art
To manufacture a device such as an LCD driving integrated circuit to which high voltage is applied, a process for forming a deep well is performed prior to defining an active region on a semiconductor substrate. Conventionally, a well drive-in process is used at a high temperature for a long period of time after implanting ions into the semiconductor substrate, thereby realizing a high breakdown voltage. In a conventional well forming process, when a step between the active region and the deep well is not formed on the semiconductor substrate, misalignment problems appear during a photolithography process, and the active region may not be properly defined.
To solve the above and related problems, in the conventional method for manufacturing the high voltage semiconductor device, a photoresist layer is formed on the semiconductor substrate by using a photolithography process before defining the active region on the semiconductor substrate. Then, the semiconductor substrate is etched to form a trench by using the photoresist layer as a mask to form a step in a subsequent process. The step formed by the trench is then used as an align key until an align key pattern is formed. However, in the prior art, the additional photolithography process for forming the align key before defining the active region increases the costs of manufacturing the device.
SUMMARY OF THE INVENTION
It is an aspect of the present invention to provide a semiconductor device for manufacturing a high voltage device capable of attaining high breakdown voltage by providing a precise alignment in defining an active region on a semiconductor substrate having a deep well.
It is another aspect of the present invention to provide a method for manufacturing a semiconductor device to form an align key that provides a precise alignment in a deep well forming process before defining an active region, thereby defining the active region without using an additional photolithography process.
According to a first embodiment of the present invention, a semiconductor device includes an align key formed of a first recess having a first depth from a surface of a semiconductor substrate in a scribe line region of the semiconductor substrate and a second step portion formed of a second recess having a second depth from the surface of the semiconductor substrate in a well region of the semiconductor substrate, wherein the second depth is less than or equal to the first depth.
Here, the well region is doped by a P-type dopant, and the well region has a well junction depth of about 1 to 12 &mgr;m.
The second recess includes an active region and an isolating region for defining the active region, wherein the isolating region is a trench region or a local oxidation of silicon (LOCOS) isolating region.
According to a further embodiment of the present invention, a semiconductor device includes an align key formed of a first recess having a first depth from a surface of a semiconductor substrate in a scribe line region of the semiconductor substrate, a second step portion formed of a second recess having a second depth from the surface of the semiconductor substrate in a first well region of the semiconductor substrate, and a third step portion formed of a third recess having a third depth from the surface of the semiconductor substrate in a second well region of the semiconductor substrate, wherein the third depth is smaller than the first depth.
It is preferable that the depth of the third recess is the same as the depth of the second recess.
The first well region is a P-well region, and the second well region is a pocket P-well region.
In addition, the second and third recesses include active regions and isolating regions for defining the active regions, respectively, wherein the isolating regions are trench regions or LOCOS isolating regions.
According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes forming an N-well on a P-type silicon substrate having a scribe line region and a device region. A P-type dopant is first implanted into a portion of the scribe line region and into a first region of the device region on the silicon substrate having the N-well. First oxide layers having a predetermined thickness are formed on the portion of the scribe line region and the first region by oxidizing a surface of the silicon substrate. A P-well is formed in the first region by diffusing the P-type dopant, which is implanted into the first region, into the silicon substrate having the first oxide layer. A first step portion is formed on the surface of the silicon substrate in the scribe line region by removing the first oxide layer formed in the scribe line region. A second step portion is formed on the surface of the P-well by removing the first oxide layer formed in the first region. An align key is formed in the scribe line region by using the first step portion.
It is preferable that the P-type dopant is boron ions in the first implanting process, and the first oxide layer has a thickness of about 500 to 5000 Å.
In addition, the P-well has a junction depth of about 1 to 12 &mgr;m from the surface of the silicon substrate in forming the P-well.
It is preferable that removing the first oxide layer formed in the scribe line region and removing the first oxide layer formed in the first region are performed by a wet etching process, respectively.
It is preferable that removing the first oxide layer for forming the first and second step portions are simultaneously performed.
According to this embodiment, the method further includes forming a first ion implantation mask pattern, which exposes only the portion of the scribe line region and the first region after forming the N-well and before the first implanting the P-type dopant. Here, the first ion implantation mask pattern is formed of a silicon nitride layer.
The method further includes second implanting a P-type dopant into the portion of the scribe line region and a second region of the device region, on the silicon substrate having the first and second step portions, before forming the align key. Thereafter, second oxide layers having a predetermined thickness are formed on the first step portion in the scribe line region and on the second region by oxidizing the surface of the silicon substrate. A pocket P-well is formed in the second region by diffusing the P-type dopant, which is implanted into the second region, into the silicon substrate having the second oxide layers. An align key forming step portion is formed on the silicon substrate surface in the scribe line region by removing the second oxide layer from the first step portion. Next, a third step portion is formed on the surface of the pocket P-well by removing the second oxide layer from the second region.
It is preferable that the pocket P-well has a junction depth of about 1 to 12 &mgr;m from the surface of the semiconductor, which is smaller than the junction depth of the P-well, in forming the pocket P-well.
It is preferable that removing the second oxide layer from the first step portion and removing the second oxide layer from the second region are formed by a wet etching process, respectively. It is preferable that removing the second oxide layer for forming the align key forming step portion and removing the second oxide layer for forming the third step portion are performed simultaneously.
It is preferable that a portion of the first oxide layer is removed for remaining a first oxide layer remaining layer having a predetermined thickness in the portion of the scribe line
F. Chau & Associates LLC
Munson Gene M.
Samsung Electronics Co. LTD
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