Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1998-04-22
2002-08-27
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S640000, C257S641000, C257S644000, C257S758000, C257S760000
Reexamination Certificate
active
06441467
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device (hereinafter simply referred to as semiconductor device) for use in, for example, a liquid crystal driver or the like, and more particularly, relates to an electrode pad structure of a semiconductor device.
BACKGROUND OF THE INVENTION
Conventionally, semiconductor chips (semiconductor devices) featuring a double metal structure have been mass-produced, and most of the semiconductor chips of this type are arranged so that each includes an electrode pad
70
in an area other than a circuit element area therein, as shown in FIG.
19
.
More specifically, for example, a silicon oxide film (hereinafter referred to as CVD-silicon oxide film)
55
formed by the low-pressure chemical vapor deposition (CVD) method and a boron phospho-silicate glass (BPSG) film
56
are laminated on a silicon substrate
51
in this order. On the BPSG film
56
, a barrier metal layer
58
and a first metal layer
59
are provided in this order as wiring materials.
The first metal layer
59
is made of aluminum or aluminum alloy containing silicon or copper siliside. However, in the case where aluminum or aluminum-alloy wires are solely provided, the liability of the device is impaired by halation occurring in a photo resist process, stress migration due to thermal stress, or the like. Therefore, in the case where it is formed to a thickness of 1 &mgr;m or less, the first metal layer
59
is deposited on the barrier metal layer
58
made of a refractory metal such as titanium, tungsten, or titanium-tungsten, or silicide of such refractory metal, or a refractory metal oxinitride.
On the first metal layer
59
, an interlayer insulating film
60
which is generally composed of a first interlayer insulating film
60
a
, a second interlayer insulating film
60
b
, a third interlayer insulating film
60
c
. The first interlayer insulating film
60
a
and the third interlayer insulating film
60
c
are films made of a silicon compound, such as silicon oxide films or silicon nitride films. The second interlayer insulating film
60
b
is formed by the spin-on-glass (SOG) method with which unevenness caused as a result of depositing the first metal layer
59
are eliminated, so that a flat surface is obtained.
A second metal layer
64
is provided on the first metal layer
59
with a barrier metal layer
63
therebetween, in a through hole formed in the interlayer insulating film
60
. In other words, in the through hole, the interlayer insulating film
60
for insulation does not exist between the first metal layer
59
and the second metal layer
64
.
On the interlayer insulating film
60
and the second metal layer
64
, there is provided a passivation film
65
(
65
a
and
65
b
) made of phospho-silicate glass (PSG) or silicon nitride. According to the bonding method such as the inner lead bonding (ILB) method, as shown in
FIG. 19
, a barrier metal layer
66
made of a refractory metal such as titanium-tungsten is formed on the passivation film
65
(
65
a
and
65
b
) and on the second metal layer
64
, and further, a gold bump
67
is formed on the barrier metal layer
66
.
Incidentally, a semiconductor chip which is formed by providing an electrode pad
70
on an active element
50
of an electric circuit as shown in
FIG. 20
, i.e., by “the area pad technique”, is recently mass-produced. By this technique whereby the electrode pad
70
is formed on the active element
50
, a portion below the pad which has not been utilized is now effectively utilized, thereby allowing reduction of the size of the chip. Besides, the electrode pad
70
is provided in any area of the chip, whereby the freedom degree relating to the design of the semiconductor chip is raised. The following description will explain the wafer manufacturing process of the semiconductor chip of this type, while referring to FIGS.
20
and
21
(
a
) through
21
(
d
).
First, as shown in FIG.
21
(
a
), a silicon oxide film
52
is formed on a silicon substrate
51
, and a polysilicon film
53
as a conductive layer is formed on the silicon oxide film
52
, so that the polysilicon film
53
constitutes a gate electrode. Then, as shown in FIG.
21
(
b
), diffusion layers
54
a
and
54
b
are formed in the silicon substrate
51
, and thereafter, a CVD-silicon oxide film
55
is formed by the low-pressure CVD method.
Subsequently, as shown in FIG.
21
(
c
), a BPSG film
56
is formed at a normal pressure on the CVD-silicon oxide film
55
, and then, the CVD-silicon oxide film
55
and the PBSG film
56
are photo-etched, so that contact holes
57
a
and
57
b
are formed. Thereafter, by the sputtering method, barrier metal layers
58
a
and
58
b
made of titanuim-tungsten or the like, first metal layers
59
a
and
59
b
for metal wiring, which are made of aluminum or aluminum alloy such as aluminum-silicon, aluminum-coppersilicon, or the like. Then, dry-etching is conducted with respect to the barrier metal layers
58
a
and
58
b
, and the first metal layers
59
a
and
59
b
, to obtain wires desirably arranged.
Next, as shown in FIG.
21
(
d
), (1) a first interlayer insulating layer
60
a
composed of a silicon oxide film, a silicon nitride film, or the like, (2) a second interlayer insulating film
60
b
composed of a film formed by the SOG method (hereinafter referred to as an SOG film) or the like, and (3) a third interlayer insulating film
60
c
composed of a silicon oxide film, a silicon nitride film, or the like, are laminated in this order on the PBSG film
56
and the first metal layer
59
a
and
59
b
, so that an interlayer insulating film
60
having a trilaminar structure is formed.
The reason why the second interlayer insulating film
60
b
is provided between the first interlayer insulating film
60
a
and the third interlayer insulating film
60
c
, whereby these three layers constitutes the interlayer insulating film
60
, is that gas such as steam from, for example, the SOG film as the second interlayer insulating film
60
b
, upon heat application thereto in the manufacturing process, would be prevented from intruding into the upper and lower layers. In the case where the silicon oxide films or the silicon nitride films are not provided so as to sandwich the SOG film, the gas may cause leakage (this phenomenon is hereinafter referred to as leakage defect).
Note that, to block the gas generated from the SOG film, the silicon nitride film which has a gas blocking property superior to that of the silicon oxide film is preferably used. However, if the SOG film is provided between the silicon nitride films, the interlayer insulating film
60
might be swollen due to gas pressure in some cases, and in the worst case, the interlayer insulating film
60
cannot be formed.
Subsequently, after forming a through hole in the interlayer insulating film
60
as shown in
FIG. 20
, a barrier metal layer
63
made of titanium-tungsten and a second metal layer
64
made of aluminum or an aluminum alloy are formed thereon as a pad metal and a wire, respectively.
Thereafter, the passivation film
65
(
65
a
and
65
b
) made of PSG or silicon nitride is formed at a predetermined position on the second metal layer
64
in a manner such that the passivation film
65
may not be damaged upon bonding. Here, as shown in a plan view of in
FIG. 22
, an opening is formed in the passivation film
65
(
65
a
and
65
b
) so that an edge
65
c
of the opening (hereinafter referred to as an opening edge
65
c
) is positioned at a distance of 2.5 &mgr;m to 10&mgr;m toward inside from an edge
64
a
of the second metal layer
64
. In the case where gold wires or aluminum alloy wires are bonded to the second metal layer
64
as the pad metal by the wire bonding method, the process ends with this step, and the semiconductor chip wafer is completed.
On the other hand, in the case where the ILB method is used as the bonding method, a barrier metal layer
66
made of a refractory metal such as titanium or titanium-tungsten is deposited on the second metal layer
64
Chikawa Yasunori
Nakamura Nakae
Nakata Yukinori
Ono Atsushi
Sakaguchi Nobuhisa
Loke Steven
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
Vu Hung Kim
LandOfFree
Semiconductor device having active element connected to an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having active element connected to an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having active element connected to an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2879153