Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond
Reexamination Certificate
2002-06-17
2003-09-16
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Wire contact, lead, or bond
C257S776000
Reexamination Certificate
active
06621171
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technique for layout of a circuit in a semiconductor device.
2. Description of the Background Art
FIG. 10
shows a layout of a conventional semiconductor device
200
A. A block
201
is surrounded by a wiring area
202
and includes a RAM (random access memory)
201
a
, a ROM (read only memory)
201
b
, a CPU (central processing unit)
201
c
and a peripheral circuit
201
d
. A plurality of bonding pads
202
a
are arranged in the wiring area
202
, to be connected to the foregoing components in the block
201
by wires not shown.
FIG. 11
shows a layout of another conventional semiconductor device
200
B having a greater storage capacity than that of the semiconductor device
200
A. The semiconductor device
200
B differs from the semiconductor device
200
A in that the RAM
201
a
and-the ROM
201
b
of the device
200
A are replaced with a RAM
201
d
and a ROM
201
e
, respectively. The RAM
201
d
and the ROM
201
e
are respectively greater than the RAM
201
a
and the ROM
201
b
in storage capacity and thus in occupying area in the layout.
As generally known, a RAM or ROM having a greater storage capacity occupies a greater area. In accordance with conventional practices, when it becomes necessary to increase the storage capacity of the semiconductor device
200
A which has already been designed, the semiconductor device
200
B in which the area of the block
201
is increased while keeping the rectangular shape thereof is newly designed. In such case, the semiconductor device
200
B would unavoidably include an unused area in the block
201
which is larger than an unused area in the block
201
of the semiconductor device
200
A by an area
500
as shown in FIG.
11
. Further, the increase of the area of the block
201
itself results in an increase of the area of the wiring area
202
surrounding the block
201
.
SUMMARY OF THE INVENTION
In order to solve the above-noted problems, it is therefore an object of the present invention to lower an increase of unused area or wiring area in a semiconductor device, which is caused due to addition or enhancement of a function of the semiconductor device without significantly changing a layout of the device which has been previously designed.
A semiconductor device according to the present invention includes a first semiconductor region, a second semiconductor region, a wiring area and at least one wire. In the first semiconductor region, at least one first circuit is placed. In the second semiconductor region, at least one second circuit connected to the at least one first circuit is placed. The wiring area includes a plurality of pads connected to the at least one first circuit and surrounds the first semiconductor region. The at least one wire is laid across said wiring area at a single position between two adjacent ones of the plurality of pads per portion of the wiring area which is sandwiched between the first and second semiconductor regions. The at least one wire connects the at least one first circuit and the at least one second circuit to each other.
There is no need for significantly changing a layout of the first semiconductor region when the second circuit is further provided in addition to the first circuit, position of which has already been determined in the first semiconductor region. This lowers an increase of the area of the first semiconductor region as well as an increase of the area of the wiring area surrounding the first semiconductor region. Further, the wire is laid across the wiring area at a single position per portion sandwiched between the first and second semiconductor regions. This also lowers the increase of the area of the first semiconductor region, and suppresses characteristics variation of the first semiconductor region which is likely to occur if the second semiconductor region is modified in many ways.
Preferably, the at least one wire is electrically broken while no request for access to the second circuit from the first circuit is present.
It is possible to avoid a situation in which although access to the second circuit is unnecessary, a wire capacitance is unwantedly applied to the first circuit. This improves an operation speed of the first circuit of the semiconductor device.
Matsubara Toshiyuki
Matsui Hideo
Takahashi Hiroki
Fahmy Wael
Farahani Dana
Mitsubishi Denki & Kabushiki Kaisha
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