Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated...
Reexamination Certificate
2002-03-13
2003-09-02
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Reexamination Certificate
active
06614091
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices, and more particularly, to a semiconductor device having a wire bond pad and method therefor.
BACKGROUND OF THE INVENTION
In Integrated Circuit (IC) manufacturing it is important for the integrated circuit die to be as small as possible to reduce cost. Wire bonding is a widely used method to connect a semiconductor die having electrical circuitry to a pin on a component package. A bond pad is an electrically conductive metal area on the surface of the IC. Even though improved technology has allowed reduced integrated circuit size, the wire bonding pad dimensions have not scaled as quickly. Therefore, bond pads consume a greater percentage of the overall circuit area. This has also reduced the area available on the IC for routing power busses in the metal layer from which the bond pads are formed.
Copper is now commonly used for interconnects in integrated circuits. However, because of problems wire bonding to copper, a wire bond pad for copper interconnect technologies often utilizes an aluminum layer to cap the exposed copper wire bond pad. This aluminum cap is added to allow use of the same wire bonding tools and processes used in aluminum interconnect technologies.
FIG. 1
illustrates a cross-sectional view of a semiconductor device
10
having a wire bond pad
13
in accordance with the prior art. Semiconductor device
10
includes a silicon substrate
19
, interconnect region
20
, passivation layer
15
and wire bond pad stack
13
. Active circuitry is formed in silicon substrate
19
. Interconnect region
20
includes copper layers
21
,
22
, and
23
, and interlevel via layers provide electrical connections between the copper layers
21
,
22
, and
23
and the active circuitry of substrate
19
. In multi-layer metal copper technology the copper portion
12
of the wire bond pad stack
13
is formed from the final, last or top layer
21
of the copper interconnect region
20
. A relatively large opening, 50-100 microns (&mgr;m) in both width and height, is cut in the final IC passivation layer
15
to expose the copper pad
12
. An aluminum cap
14
is then deposited on the copper pad
12
, stepping up onto passivation layer
15
around the perimeter of the wire bond region.
As stated above, on a chip scale, bond pads are quite large. In a typical chip design, I/O (input/output) pad cells are placed in a ring around the periphery of the chip. Bond pads typically cover one half to one quarter of this I/O ring area. Large metal power supply busses are typically routed in this I/O ring as well. In many chip designs, electrical performance may be limited by resistance in these busses. One solution to the bus resistance problem would be to add an additional copper metal layer to the process flow, providing another layer in the bus metal stack, but this entails added cost. Alternately, the I/O ring area could be increased to provide more area for routing power busses, but this also adds cost.
Thus, there is a need for a wire bond pad and power and ground bus that can reduce the severity of the above problems without added cost.
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Downey Susan H.
Hall Geoffrey B.
Miller James W.
Hil Daniel D.
Le Thao
Motorola Inc.
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