Semiconductor device having a triple gate transistor and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – With current flow along specified crystal axis

Reexamination Certificate

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C257S627000, C257SE29004

Reexamination Certificate

active

11024616

ABSTRACT:
In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.

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Maeda, Shigenobu,et al., “Negative Bias Temperature Instability in Triple Gate Transistors,” IEEE 04CH37533 42ndAnnual International Reliability Physics Symposium, Phoenix, 2004, pp. 8-12.
Lemme, M., et al., “Subthreshold Charactericstics of p-type Triple-Gate MOSFETs,” Advanced Microelectronic Center Aachen (AMICA), AMO GmbH, Huyskensweg 25, 52074 Aachen, Germany and Institut für Halbleitertechnik, RWTH-Aachen, Sommerfeldstr. 24, 52074 Aachen.
“Crystal Planes in Semiconductors,” Brigham Young University, www.ee.byu.edu/cleanroom/EW—orientation.phtml.

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