Semiconductor device having a trench isolation structure and an

Details Semiconductor device having a trench isolation structure and an Semiconductor device having a trench isolation structure and an

1997-12-12

2000-07-18

Loke, Steven

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

438401, H01L 23544, H01L 2176

Patent

active

060911581

ABSTRACT:
A resist pattern (51) is formed only on buried silicon oxide films (2) on the whole surface of an alignment mark area (11A) and a trench (10C). With the resist pattern (51), preetching is performed by dry etching, to remove the silicon oxide film (2) on the whole of a memory cell area (11B) and part of a peripheral circuit area (11C) by a predetermined thickness. After removing the resist pattern (51), a silicon oxide film (3) and a silicon nitride film (4) are removed by CMP polishing, to provide a height difference between the highest portion and the lowest portion of the silicon oxide film (2A) which serves as an alignment mark. Thus, a semiconductor device with trench isolation structure which achieves a highly accurate alignment without deterioration of device performance and a method for manufacturing the semiconductor device can be provided.

REFERENCES:
patent: 5316966 (1994-05-01), Van Der Plas et al.
patent: 5369050 (1994-11-01), Kawai
patent: 5578519 (1996-11-01), Cho
patent: 5893744 (1999-04-01), Wang

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