Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-09-27
2003-09-09
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S513000, C257S368000
Reexamination Certificate
active
06617662
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device and a method for fabricating the same, and more specifically to a trench isolation structure of a semiconductor device and a method for fabricating the same.
2. Description of the Related Art
As integration density of semiconductor integrated circuits increases, circuit components such as transistors are formed closer to each other and reliability of the circuits can be reduced unless effective isolation techniques for separating devices such as MOS transistors are employed. A trench isolation technique which can form an isolation region having a narrow width is widely used in the manufacture of a highly integrated semiconductor device.
However, the trench isolation method inherently suffers from problems such as substrate damage caused from the trench etching process, oxidation of the semiconductor substrate in sidewalls of the trench during a subsequent oxidation process, or another physical-thermal stress.
To suppress the stress arising from the oxidation process, a technique has been proposed in which a thermal oxidation film is formed in inner walls of trenches after forming a trench in a semiconductor device, and then a nitride liner is formed on the thermal oxidation film. U.S. Pat. No. 5,447,884 discloses the aforementioned method performing a trench isolation in which oxidation of the inside of the trench is prevented by forming a nitride liner on a thermal oxidation film.
However, the use of the nitride liner causes other problems. Electrical charges can be trapped in the inside of the nitride liner, or into a boundary region between the nitride liner and the thermal oxidation film in the trench, so that charges electrically opposite to the trapped charges are coupled at sidewalls of the trenches. In PMOS, for instance, if the nitride liner traps electrons, holes electrically coupled with the trapped electrons are collected in the trench sidewalls, resulting in a lower threshold voltage. As a result, the transistor (i.e., the PMOS transistor) can be non-intentionally or falsely triggered to turn on at operation voltage lower than a predetermined threshold voltage.
In addition, while removing a pad nitride film composing an etch mask for patterning the trenches, a part of the nitride liner formed in the trench is concurrently etched away with pad nitride film, and thereby recesses, and so-called “dents” are created along the trench sidewalls.
Meanwhile, U.S. Pat. No. 5,940,717, entitled “Recessed Shallow Trench Isolation Structure Nitride Liner and Method for Making Same”, filed on Oct. 30, 1998 discloses a method of forming a nitride liner which is recessed in the inside of the trench to reduce the generation of the charge trap at the nitride liner.
FIG. 1
is a cross-sectional view of a trench isolation structure. The structure shown includes a semiconductor substrate
100
, a thermal oxide film
112
, a pad oxide film
106
, a nitride liner
114
, and a trench fill insulating material
702
. As shown in
FIG. 1
, the thermal oxide film
112
is disposed inside the trench, and the nitride liner
114
is disposed on the thermal oxidation film
112
. However, the nitride liner
114
is recessed to a predetermined depth in the inside of the trench from a top surface of the substrate
100
. Namely, the nitride liner
114
is recessed downward along the trench sidewall and below the channel region, thereby preventing charge trapping in the channel region. Further, the trench fill insulating material
702
is formed to completely fill the trench on the thermal oxidation film
112
and the nitride liner
114
. The nitride liner
114
serves to prevent a bulk expansion caused by oxidation in the inside of the trench, a stress increment of a silicon substrate, and a defection therefrom. However, since the nitride liner
114
is not formed on an upper part of the trench, an inner wall of upper part of the trench may be oxidized, resulting in failure to obtain the original function of the nitride liner. Thus, a need exists for a semiconductor device having a trench isolation structure for effectively solving the aforementioned problems.
SUMMARY OF THE INVENTION
A semiconductor device is provided which includes: a trench formed in a semiconductor substrate to confine a plurality of active regions; an insulating material deposited to fill the trench and the insulating material having a portion extending from the trench to above the semiconductor substrate; and a trench oxidation preventive film formed on the insulating material.
The semiconductor device preferably further includes: a gate line extending in one direction on the semiconductor substrate having the trench oxidation-preventive film; and a sidewall spacer formed a sidewall of the gate line, wherein the trench oxidation-preventive film is disposed on the insulating material and disposed under the gate line and the sidewall spacer.
According to a preferred embodiment of the invention, the insulating material includes: a first oxide film formed on an upper edge of the active region, and a bottom and a sidewall of the trench; and a second oxide film formed on the first oxide film to completely fill the trench. The first oxide film is a thermal oxide film and the second oxide film is a chemical vapor deposition (CVD) oxide film.
A method for forming a trench isolation is also provided which includes the steps of: forming a planarization stop layer on a semiconductor substrate on which a pad oxide layer is formed; forming a trench in the semiconductor substrate by etching sequentially a part of the planarization stop layer, a part of the pad oxide film, and a part of the semiconductor substrate; performing a thermal oxidation process for the semiconductor substrate in which the trench is formed; filling the trench with a trench fill insulating material in which the thermal oxidation process is performed; planarizing the trench fill insulating material such that the planarization stop layer is exposed; recessing the trench fill insulating material to under the planarization stop film; and forming a trench oxidation-preventive film on the recessed trench fill insulating material.
According to a preferred embodiment of the invention, the level of the trench oxidation-preventive film is substantially even with an upper surface of the planarization stop film after planarizing. The planarization stop film is made of a silicon layer, and the trench oxidation-preventive film is made of a silicon nitride film.
A method for forming a trench isolation is also provided which includes the steps of: forming a planarization stop layer on a semiconductor substrate on which a pad oxide film is formed; forming a trench by etching sequentially a part of the planarization stop film, a part of the pad oxidation film, and a part of the semiconductor substrate; forming a thermal oxide film on a bottom and a sidewall of the trench, and on a sidewall and a top surface of the planarization stop film; filling the trench with a trench fill insulating material on the thermal oxide film to completely fill the trench; planarization the trench fill insulating material such that the planarization stop film is exposed; recessing the planarized trench fill insulating material under the planarization stop film; forming a trench oxidation-preventive film on the recessed trench fill insulating material.; and removing the planarization stop film and the pad oxide film.
According to a preferred embodiment of the present invention, the planarization stop film is made of a silicon film and the trench oxidation-preventive film is made of a silicon nitride film. The step of filling the trench is performed in a same facility for the step of the forming the thermal oxide film. The step of recessing the planarized trench fill insulating material exposes a sidewall of the planarization stop film, and recesses substantially to an interface between the planarization stop film and the pad oxidation film.
According to a preferred embodiment of the present
F. Chau & Associates LLP
Loke Steven
Owens Douglas W.
Samsung Electronics Co. LTD
LandOfFree
Semiconductor device having a trench isolation structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having a trench isolation structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a trench isolation structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3000996