Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1994-05-26
1995-07-18
Wojciechowicz, Edward
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257517, 257519, 257622, H01L 2906
Patent
active
054344476
ABSTRACT:
A device-isolating trench having a taper at its upper portion is formed in a silicon semiconductor substrate. Then, a silicon oxide film is formed on the inner wall of the trench and the surface of the semiconductor substrate near the trench by an oxidizing method, and polycrystalline silicon is buried in the trench.
REFERENCES:
patent: 5100822 (1992-03-01), Mitani
Y. Tamaki et al., Evaluation of Dislocation Generation in U-Groove Isolation, Journal of the Electrochemical Society, vol. 135, No. 3, Mar. 1988, pp. 726-730.
A. Hayasaka et al., U-Groove Isolation Technique for High Speed Bipolar VLSI's, IEDM, 1982.
L. O. Wilson, Oxidation of Curved Silicon Surfaces, Journal of the Electrochemical Society, vol. 134, No. 2, pp. 481-490, Feb. 1987.
K. Imai et al., Decrease in Trenched Surface Oxide Leakage Currents By Rounding Off Oxidation, Japanese Journal of Applied Physics, Supplements 18th Conference on Solid State Devices, pp. 303-306, 1986.
Miyashita Naoto
Takahashi Koichi
Kabushiki Kaisha Toshiba
Wojciechowicz Edward
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