Patent
1989-04-03
1991-10-15
Wojciechowicz, Edward J.
357 86, 357 89, H01L 2978
Patent
active
050578847
ABSTRACT:
A semiconductor substrate has on its major surface a N.sup.- drain region, within which a P base region is selectively formed. In the P base region is formed a P.sup.+ base region which has a higher impurity concentration than that of the P base region. A source region is selectively formed across and within the P base region and P.sup.+ base region. The source region has a lightly doped N source region and a heavily doped N.sup.+ source region. The N.sup.+ source region is entirely formed within the P.sup.+ base region so as not to form an N.sup.+ P junction which is high in emitter injection efficiency and thereby to make a parasitic transistor hard to operate. Furthermore, the N source region is formed smaller in depth than the P.sup.+ source region so as to decrease the base spreading resistance of the parasitic transistor and thereby to make the parasitic transistor hard to operate. A gate electrode is formed over a channel region, which is a portion of the P base region that is sandwiched between the N.sup.- drain region and the N source region and exposed to the major surface of the substrate, with a gate insulating layer interposed therebetween.
REFERENCES:
patent: 4729001 (1988-03-01), Haskell
Suzuki Kenji
Tanabe Hirohito
Kabushiki Kaisha Toshiba
Wojciechowicz Edward J.
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