Semiconductor device having a specified terminal layout pattern

Details Semiconductor device having a specified terminal layout pattern Semiconductor device having a specified terminal layout pattern

2011-05-03

2011-05-03

Sandvik, Benjamin P (Department: 2893)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257SE23019, C257SE23142, C257SE23145, C257SE23151, C257SE21575, C257SE21627, C438S129000

Reexamination Certificate

active

07936071

ABSTRACT:
A semiconductor device comprises a semiconductor substrate that is provided with an integrated circuit; a multi-layered member that is installed in the semiconductor substrate, including a plurality of conductive members and an insulation member; and an external terminal formed on a part of the surface of the multi-layered member. A pair of the conductive members contacts with the upper surface and the lower surface of the insulation member directly under the external terminal, includes a portion where the conductive members are overlapped each other, and are electrically coupled to each other.

REFERENCES:
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patent: 5751065 (1998-05-01), Chittipeddi et al.
patent: 6316801 (2001-11-01), Amanuma
patent: 6417530 (2002-07-01), Jung
patent: 6765773 (2004-07-01), Reiner
patent: 2002/0000579 (2002-01-01), Aoyama
patent: 2004/0135256 (2004-07-01), Takahashi et al.
patent: 09-283525 (1997-10-01), None
patent: 2002-198374 (2002-07-01), None
patent: 2003-124336 (2003-04-01), None

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