Semiconductor device having a shallow trench isolation and...

Details Semiconductor device having a shallow trench isolation and... Semiconductor device having a shallow trench isolation and...

2006-05-09

2006-05-09

Blum, David S. (Department: 2813)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C438S322000

Reexamination Certificate

active

07041563

ABSTRACT:
The present invention includes a semiconductor device having a shallow trench isolation and a method of fabricating the same. The semiconductor device includes a gate electrode being arranged to cross over the active region. An oxide pattern is interposed between the active region and the edge of the gate electrode. The oxide pattern defines a channel region under the gate electrode. A lightly doped diffusion layer is formed in the active region downward and outward from the oxide pattern, and a heavy doped diffusion layer is formed in a predetermined region of the active region and surrounded by the lightly doped diffusion layer. In the method of fabricating the semiconductor substrate, a trench isolation layer is formed at a predetermined region of a semiconductor substrate to define an active region. A pair of preliminary lightly doped diffusion layers are formed in a line to cross over the active region. Then, oxide patterns are formed to cover at least the preliminary lightly doped diffusion layers. The oxide pattern defines a channel region. A gate oxide layer is formed on the channel region and a gate electrode is formed to cover the channel region and to cross over the active region. The edge of the gate electrode is over the oxide pattern. A heavy doped diffusion layer is formed in the active region of both regions of a gate electrode and shallower than the lightly doped diffusion layer.

REFERENCES:
patent: 5384476 (1995-01-01), Nishizawa et al.
patent: 5716866 (1998-02-01), Dow et al.
patent: 6413823 (2002-07-01), Wu et al.

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