Semiconductor device having a reverse bias voltage generator

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

3072965, 307443, H03K 301, H03K 1716, G11C 1100

Patent

active

049964461

ABSTRACT:
An output circuit of a semiconductor circuit has a reverse bias voltage generator which comprises a ring oscillating circuit, a reverse bias voltage generating circuit and a switching circuit. The output circuit is of the type having first and second output N-(P-)channel MOS transistors connected in series, an output terminal being provided at the intermediate position of the transistors. The ring oscillating circuit is activated for oscillation only when an ouptut enabling signal is of a zero potential indicative of disabling outputting of an input data signal. The reverse bias voltage generating circuit generates a reverse bias voltage lower (higher) than the ground potential based on the oscillation output of the oscillating circuit. The switching circuit supplies a reverse bias voltage to the gate of the first output N-(P-)channel MOS transistor only when a bias instruction signal, i.e., a complementary signal of the output enabling signal, is of a positive (negative) potential, whereby the occurrence of ionization current in the first output N-(P-)channel MOS transistor can be effectively prevented even when a negative (positive) voltage is applied to the output terminal.

REFERENCES:
patent: 4446384 (1984-05-01), Taira
patent: 4455628 (1984-06-01), Ozaki et al.
patent: 4571509 (1986-02-01), Tobita
patent: 4697252 (1987-09-01), Furuyama et al.
patent: 4920280 (1990-04-01), Cho et al.

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