Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-01-05
2003-04-01
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S614000, C257S635000, C257S637000, C257S734000, C257S743000, C257S748000, C257S750000, C257S752000, C257S760000, C438S622000, C438S624000
Reexamination Certificate
active
06541863
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to fabricating integrated circuit devices and, more particularly, to the formation of metallization layers exhibiting reduced signal processing time.
2. Description of the Related Art
In the field of semiconductor production, there is a tendency to reduce the dimensions of semiconductor devices in an integrated circuit. At the same time, the clock frequency of a digital circuit, such as a CPU, is routinely increased from one design generation to a subsequent design generation.
As the clock frequency rises, however, the electrical characteristics of the various metallization layers within the integrated circuit steadily gain in importance. High resistivities of the contacts and wiring lines connecting the semiconductor devices, as well as high capacitances resulting from those contacts and lines, increase the fall and rise times of the electrical signals that are transmitted in the integrated circuit, thereby impairing device performance.
In this respect, it is also important to consider the stray capacitances of adjacent contacts and wiring lines. Increased capacitance between adjacent conductors is undesirable because it may delay signal propagation along the conductors, and it may result in increased power consumption by the integrated circuit device, as this capacitance must be charged-up during each operating cycle. As the capacitance of two conductors is inversely proportional to the distance between the conductors, reducing the device dimensions inevitably leads to an increase of the stray capacitance of adjacent conductors. Moreover, in very large scale integration (VLSI) circuits in which multiple metallization layers are formed, the vertical distance between adjacent layers can not be arbitrarily enlarged to reduce the capacitance between these layers, since a maximum vertical distance is determined by the aspect ratio of the via holes connecting two adjacent metallization layers. Exact control of the dimensions of the via holes, however, is necessary to obtain narrowly spaced apart vias for reduced circuit dimensions as well as for a sufficient thickness of the vias to guarantee a low electrical resistivity of the via.
The present invention is directed to a method for solving, or at least reducing the effects of, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is directed to a semiconductor device having reduced signal processing time and a method of making same. In one illustrative embodiment of the present invention, the device is comprised of a layer of porous material having a density ranging from approximately 20-80% of the density from which the porous material is made, and a plurality of conductive interconnections formed in the layer of material.
One illustrative embodiment of the present invention comprises providing a layer of material having an original density, reducing the density of the layer of material to approximately 20-80% of the original density of the starting material, forming at least one opening in the layer with a reduced density, and forming a conductive interconnection in the opening.
REFERENCES:
patent: 4380865 (1983-04-01), Frye et al.
patent: 4628591 (1986-12-01), Zorinsky et al.
patent: 4866009 (1989-09-01), Matsuda
patent: 5103288 (1992-04-01), Sakamoto et al.
patent: 5494858 (1996-02-01), Gnade et al.
patent: 5561318 (1996-10-01), Gnade et al.
patent: 5691238 (1997-11-01), Avanzino et al.
patent: 5744865 (1998-04-01), Jeng et al.
patent: 5821621 (1998-10-01), Jeng
patent: 5847443 (1998-12-01), Cho et al.
patent: 5870076 (1999-02-01), Lee et al.
patent: 5904576 (1999-05-01), Yamaha et al.
patent: 5914183 (1999-06-01), Canham
patent: 6017811 (2000-01-01), Winton et al.
patent: 6037634 (2000-03-01), Akiyama
patent: 6090724 (2000-07-01), Shelton et al.
patent: 6265303 (2001-07-01), Lu et al.
patent: 6287936 (2001-09-01), Perea et al.
patent: 6376859 (2002-04-01), Swanson et al.
patent: 6407441 (2002-06-01), Yuan
patent: 0 333 132 (1989-09-01), None
patent: WO 98/00862 (1998-01-01), None
Poponiak et.al. “High Sheet Resistivity Resistors by the Porous Silicon”, Jun. 1975, IBM Tech Disclosure Bulletiin.
Burbach Gert
Horstmann Manfred
Wieczorek Karsten
Advanced Micro Devices , Inc.
Lee Eddie
Ortiz Edgardo
Williams Morgan & Amerson P.C.
LandOfFree
Semiconductor device having a reduced signal processing time... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having a reduced signal processing time..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a reduced signal processing time... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3073939