Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-06-29
2002-07-09
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S347000, C257S350000, C257S352000
Reexamination Certificate
active
06417558
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in the Japanese Patent Application No. Hei 11-186833 filed in Jun. 30, 1999 in Japan, to which the subject application claims priority under the Paris Convention and which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor. device structure, and more specifically to a silicon-on-insulator semiconductor device having a reduced parasitic capacitance bonding pad structure.
2. Description of the Related Art
FIG. 1A
is a cross-sectional view showing a semiconductor device having a conventional silicon-on-insulator (SOI) structure. A semiconductor device
100
in
FIG. 1A
adopts an SOI structure
102
that comprises a substrate
10
, a buried oxide layer
12
, and an active semiconductor layer (device layer)
14
. A bonding pad
24
, which is formed by opening a hole in a passivation layer
20
, is arranged on this SOI structure
102
. In the case of
FIG. 1A
, a capacitance C generated between the bonding pad
24
and the substrate
10
is represented by two series-connected capacitances. That is, as shown in
FIG. 1B
, the capacitance C between the bonding pad
24
and the substrate
10
consists of series-connected capacitances C
16
and C
12
. The capacitance C
16
is generated in a field insulating layer
16
as a capacitance insulating layer between the bonding pad
24
as an upper electrode and the active layer
14
as a lower electrode. The capacitance C
12
is generated in the buried oxide layer
12
as the capacitance insulating layer between the active layer
14
as the upper electrode and the substrate
10
as the lower electrode. As apparent from
FIG. 1B
, the capacitance C can be represented by
1
/C
=(1
/C
16
)+(1
/C
12
). (1)
In other words, the capacitance C between the bonding pad
24
and the substrate
10
can be given by
C
=(
C
16
·
C
12
)/(
C
16
+
C
12
). (2)
However, the bonding pad formed on the SOI structure
102
in the prior art contains following problems. First, as described above, there is such a first problem is that the capacitance C represented by above Eq.(2) is generated between the bonding pad
24
and the substrate
10
in
FIG. 1A
, that is, the capacitance C is parasitically generated. When an electric signal is input from an external circuit (not shown) into various semiconductor devices (not shown) formed in the active layer
14
via the bonding pad
24
, charge/discharge of the parasitic capacitance C connected to the bonding pad
24
is carried out simultaneously. Such charge/discharge of the parasitic capacitance C is repeated every time when the electric signal is input via the bonding pad
24
. Therefore, a consumption power of the semiconductor integrated circuit (not shown) formed on the SOI structure
102
is caused to increase.
Also, when a wire such as a gold wire, etc. is connected to the bonding pad
24
by the bonding, a strong mechanical impact is applied to a field insulating layer
16
formed directly under the bonding pad
24
. Therefore, there is also such a second problem that cracks are produced in the field insulating layer
16
. The cracks act as current paths between the bonding pad
24
and the active layer
14
. As a result, the cracks cause leakage currents to flow between a plurality of neighboring bonding pads
24
via the active layer
14
.
In addition, there is such a third problem that an electric signal generated due to generation of the above leakage currents is transmitted to the substrate
10
via the capacitance C
12
of the buried oxide layer
12
in FIG.
1
B. This electric signal causes the electric interference in other bonding pads and other wirings except for the bonding pad
24
and the wiring
18
in
FIG. 1A
, or the semiconductor device in the active layer
14
, etc. Then, malfunction of the semiconductor integrated circuit formed on the SOI structure
102
is caused due to such electric interference.
SUMMARY OF THE INVENTION
The present invention has been made to overcome such subjects, and it is an object of the present invention to provide a semiconductor device having a reduced parasitic capacitance bonding pad structure, capable of achieving reduced power consumption by reducing a parasitic capacitance.
It is another object of the present invention to provide a semiconductor device having a reduced parasitic capacitance bonding pad structure, capable of preventing malfunction of a semiconductor integrated circuit by suppressing a leakage current.
It is still another object of the present invention to provide a semiconductor device having a reduced parasitic capacitance bonding pad structure, capable of having high reliability for an impact effect in wire bonding.
In order to achieve the above object, according to a first aspect of the present invention, there is provided a semiconductor device having a silicon-on-insulator structure, comprising: a substrate; a first insulating layer (buried insulating layer) formed on the substrate; a first conductivity type semiconductor layer (active layer) formed on the buried insulating layer; a second insulating layer (field insulating layer) formed on the active layer; an electrode (bonding pad) formed on a part of the field insulating layer; and a semiconductor region within the semiconductor layer, the semiconductor region having a second conductivity type opposite the first conductivity type, and wherein the semiconductor region is positioned below the electrode. Here, either n-type or p-type may be selected as the first conductivity type. The second conductivity type is the p-type if the n-type is selected as the first conductivity type, otherwise the second conductivity type is the n-type if the p-type is selected as the first conductivity type. An SOI structure consisting of the substrate, the buried insulating layer, and the active layer may be formed by any one of the SIMOX method, a bonded-wafer method, and the epitaxial growth method.
Preferably, the semiconductor region should be brought into an electrically floating state, and a bottom portion of the semiconductor region should be apart by a predetermined distance from a top portion of the buried insulating layer not to directly contact. This is because, if the semiconductor region is electrically connected to other regions or comes into contact with the buried insulating layer, the leakage current is generated via the semiconductor region.
According to the first aspect of the present invention, the parasitic capacitance connected to the bonding pad can be reduced. Therefore, it is possible to reduce the capacitance that is charged/discharged every time when the electric signal is input/output via the bonding pad. As a result, consumption power of the semiconductor integrated circuit can be reduced.
Also, according to the first aspect of the present invention, the pn junction composed of the first conductivity type active layer and the second conductivity type semiconductor region is formed below the bonding pad. Therefore, even if the leakage current flows via the field insulating layer, diffusion of the leakage current can be prevented because of the presence of the pn junction.
In addition, the electric interference on other bonding pads, the devices, etc. can be reduced by reducing the above leakage current. Thus, the stable operation of the semiconductor integrated circuit can be achieved.
According to a second aspect of the present invention, the number of the semiconductor regions formed in the active layer is increased to two in the semiconductor device according to the above first aspect. That is, according to the second aspect of the present invention, there is provided a semiconductor device having a silicon-on-insulator structure, comprising: a substrate; a first insulating layer (buried insulating layer) formed on the substrate; a first conductivity type semiconductor layer (active layer) formed on the buried insulating layer;
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Tran Minh Loan
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