Active solid-state devices (e.g. – transistors – solid-state diode – Tunneling pn junction device
Reexamination Certificate
1999-04-08
2002-07-09
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Tunneling pn junction device
C257S106000, C257S019000, C257S018000, C257S046000, C438S979000
Reexamination Certificate
active
06417526
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a semiconductor device having a rectifying junction, in particular on a switching diode, comprising a semiconductor body including a substrate and a first silicon semiconductor region of a first conductivity type having a high doping concentration, and a second silicon semiconductor region of a second conductivity type, which is opposite to the first conductivity type, and having a low doping concentration and a thickness which is greater than that of the first semiconductor region, said rectifying junction being situated between the first semiconductor region and the second semiconductor region, the first semiconductor region including a sub-region containing a mixed crystal of silicon and germanium, and said first and said second semiconductor region being provided with, respectively, a first and a second connection conductor. The invention also relates to a method of manufacturing such a device.
Such a device is known from United States patent specification U.S. Pat. No. 5,342,805, published on Aug. 30, 1994. Said document discloses (see, for example,
FIG. 3
) a diode having a semiconductor body which comprises, in succession, an n-type silicon substrate with a high doping concentration, an n-type epitaxial silicon layer, which is provided thereon and which has a relatively low doping concentration, at the surface of which there is a layer of a p-type silicon having a high doping concentration, which is formed by diffusion. At the location where the diffused region and the epitaxial layer, which form, respectively, a first and a second semiconductor region, border on each other, there is a rectifying pn-junction. The substrate forms an n
+
region. Consequently, the device forms a p
+
n(n
+
) diode. Since both the p
+
region and the n
+
region are relatively thick, the profile of the charge carriers in both regions is relatively flat. As a result, diffusion currents of electrons (in the p
+
region) and of holes (in the n
+
region) are negligibly small. The current in such a diode is dominated by recombination of electrons and holes, and the current density is equal to the ratio between the overall amount of charge carriers per unit area in the n-type region and the effective service life of the charge carriers. When the diode is switched from the forward direction to the reverse direction, a depletion region has to build up, particularly in the n-type region, which involves the removal of holes. Switching typically takes place at a constant reverse current (density). In this case, the time necessary to switch off (t) the diode is proportional to the charge stored in the n-type region. If the charge carriers have a long service life, then the stored charge is large. As a result, the diode is slow. The service life of charge carriers can be reduced by introducing gold or platinum into the semiconductor body, resulting in a faster diode. In the known device, the first semiconductor region comprises, instead of or in addition to gold, a sub-region including a mixed crystal of silicon and 20% germanium, which has a thickness of 1 to 2 &mgr;m. Such a sub-region introduces a mechanical stress into the device (the mixed crystal has a lattice constant which differs from that of the rest of the device) which is so large that stress relaxation occurs, causing so-called misfit dislocations. These dislocations reduce (in the same manner as gold atoms) the service life of the (minority) charge carriers. This too results in a faster diode. The known diode has a switching time (t) of, for example, 25 nsec.
A drawback of the known device is that, although it is very fast, it is still not fast enough for specific applications, particularly for use as a switching diode for high voltages and/or high powers.
SUMMARY OF THE INVENTION
Therefore, it is an object of the invention to provide a device of the type mentioned in the opening paragraph, which has a very slow switching time, and to provide a simple method of manufacturing such a device.
To achieve this, a device of the type mentioned in the opening paragraph is characterized in accordance with the invention in that the entire first semiconductor region contains a mixed crystal of silicon and germanium, and the germanium content and the thickness of the first semiconductor region are selected so that the mechanical stress built up in the semiconductor device is smaller than or equal to the stress at which misfit dislocations are formed. It has surprisingly been found that such a diode has a much shorter switching time than the known diode. The invention is based on the following recognitions. By limiting the mechanical stress in the device by choosing a sufficiently low germanium content and/or a sufficiently small thickness of the germanium-containing layer, stress relaxation involving misfit dislocations does not occur. However, in this case the band gap of the mixed crystal of silicon and germanium is substantially smaller, not only much smaller than the band gap of silicon but also much smaller than the band gap of a relaxed mixed crystal of silicon and germanium. As a result, the concentration of minority charge carriers in the first semiconductor region, i.e. in the case of p
+
n diode electrons, is substantially increased. The reason for this being that the product of the concentration of minority charge carriers and the concentration of majority charge carriers, i.e. in this case the p-type doping concentration, is inversely exponentially dependent upon the band gap. Since the electron concentration in the vicinity of the connection conductor of the first semiconductor region is substantially zero, the increase of the electron concentration in the first semiconductor region causes a substantially increased electron-concentration gradient in said region. As a result, in the first (p
+
type) semiconductor region, the contribution of the electron-injection current to the overall current increases and may even exceed the recombination current in the second (n-type) semiconductor region. As a result, the switching time of the diode decreases. To achieve said increase of the electron concentration it is necessary, however, that the first semiconductor region is substantially entirely made of the silicon-germanium-containing material. As mentioned hereinabove, misfit dislocations are avoided by keeping the stress in the silicon-germanium region at a sufficiently low level. This is achieved by choosing the relative deviation of the lattice constant of the mixed crystal with respect to the lattice constant of the rest of the semiconductor body and/or the thickness of the silicon-germanium-containing region to be sufficiently small. Said deviation in lattice constant is directly proportional to the germanium content. The generally relatively small thickness of the first semiconductor region, which is necessary to avoid the development of misfit dislocations, has a surprising additional advantage: as a result of the small thickness of the first semiconductor region, also the gradient in the electron concentration in this region is additionally increased. This enhances the above-explained effect on the diffusion current and the recombination current. All this results in a device having a surprisingly short switching time of, for example, 3 to 9 nsec. A further important advantage of a device in accordance with the invention is that, by virtue of the absence of (misfit) dislocations, a relatively small leakage current (in the reverse direction) is achieved. The device further exhibits a relatively small voltage drop in the forward direction.
In a preferred embodiment of a device in accordance with the invention, the germanium content and the thickness of the first semiconductor region are selected so that the product of the thickness of the first semiconductor region and the relative deviation of the lattice constant of the first semiconductor region with respect to the substrate is smaller than or equal to 40 nm*percent, and preferably small
Brown Adam R.
De Boer Wiebe B.
Huizing Hendrik G. A.
Hurkx Godefridus A. M.
Peter Michael S.
Biren Steven R.
Koninklijke Philips Electronics , N.V.
Nadav Ori
Thomas Tom
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