Semiconductor device having a power down mode

Details Semiconductor device having a power down mode Semiconductor device having a power down mode

2005-03-22

2005-03-22

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S226000, C365S227000

Reexamination Certificate

active

06870790

ABSTRACT:
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

REFERENCES:
patent: 5463588 (1995-10-01), Chonan
patent: 5659519 (1997-08-01), Lee et al.
patent: 5781494 (1998-07-01), Bae et al.
patent: 5804893 (1998-09-01), Fujioka
patent: 5877652 (1999-03-01), Oh
patent: 9-161481 (1997-06-01), None

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