Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Patent
1998-09-18
2000-10-17
Thomas, Tom
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
257779, 257778, 257784, 257686, 257795, 257666, 438108, 438109, H01L 2940
Patent
active
061336378
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a semiconductor device and method for manufacturing same. More specifically, this invention relates to a semiconductor device having a plurality of semiconductor chips mounted on one another, and a method for manufacturing such a semiconductor device.
PRIOR ART
There is a conventional semiconductor device of this kind disclosed as one example in Japanese Patent Laying-Open No. H6-112402 laid open on Apr. 22, 1994. This prior art includes two IC chips connected at their surfaces through bumps and transfer-molded by a resin. In this prior art, however, resin tends to intrude into a gap between the IC chips during transfer molding, resulting in a possibility of damaging to the IC chips.
Meanwhile, there is also a technique disclosed in Japanese Patent Laying-Open No. H6-209071 laid open on Jul. 26, 1994 wherein, prior to transfer molding, a resin is filled in a gap between two IC chips. This eliminates the above-stated problem of damaging to the IC chips.
However, positive electrical connection between the IC chip is not available by any of the prior arts.
Further, there is a necessity of accurately recognizing the positions of electrodes when mounting one IC chip on the other IC chip. It is a conventional practice to image electrodes of an IC chip on a chip-by-chip basis. That is, two cameras must be used to image the electrodes of these IC chips, thus raising a problem of mounting up of cost.
SUMMARY OF THE INVENTION
Therefore, it is a primary object of this invention to provide a semiconductor device having two IC chips that are positively in electrical connection with their surfaces placed faced to each other.
It is another object of this invention to provide a method for manufacturing a semiconductor device by which manufacturing cost can be kept low.
A semiconductor device according to the present invention comprises: a first semiconductor chip having a first surface formed with a first electrode; a second semiconductor chip having a second surface formed with a second electrode to be connected to the first electrode and facing to the first surface; a bump formed on at least one of the first electrode and the second electrode; and an anisotropic conductive member interposed between the first surface and the second surface.
According to this invention, the first semiconductor chip and the second semiconductor chip are placed with their surfaces faced to each other. The bump is formed on the first electrode or second electrode, and an anisotropic conductive member is interposed between the first semiconductor chip and the second semiconductor chip. The anisotropic conductive member exhibits electrical conductivity in a thickness direction at a portion exerted by pressure. Consequently, the depression of the bump against the anisotropic conductive member provides electrical connection only between the first electrode and the second electrode, with other portions kept in insulation. Due to this, the first semiconductor chip and the second semiconductor chip are brought into electrical connection therebetween.
In one aspect of this invention, the first semiconductor chip and the second semiconductor chip at their joining portion are packaged by a first synthetic resin excellent in moisture resistance. The first semiconductor chip, the second semiconductor chip, and the first synthetic resin are packaged by a second synthetic resin that is excellent in adhesibility. Due to this, it is possible to protect the circuit elements that are less resistive to moisture, and improve the durability for the semiconductor chips.
In another aspect of this invention, the first electrode is formed with a bump while the second electrode with a recess. The recess serves to prevent the conductive particles from escaping sideways when the anisotropic conductive member is depressed by the bump. Due to this, the first semiconductor chip and the second semiconductor chip can be electrically connected therebetween more positively without increasing an amount of the conductive particle
REFERENCES:
patent: 4620215 (1986-10-01), Lee
patent: 4764804 (1988-08-01), Sahara et al.
patent: 5108950 (1992-04-01), Wakabayashi et al.
patent: 5148266 (1992-09-01), Khandros et al.
patent: 5376825 (1994-12-01), Tukamoto et al.
patent: 5523628 (1996-06-01), Williams et al.
patent: 5864178 (1999-01-01), Yamada et al.
Hikita Junichi
Miyata Osamu
Morifuji Tadahiro
Shibata Kazutaka
Yamaguchi Tsunemori
Rohm & Co., Ltd.
Thai Luan
Thomas Tom
LandOfFree
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