Semiconductor device having a plurality of cavity defined gating

Details Semiconductor device having a plurality of cavity defined gating Semiconductor device having a plurality of cavity defined gating

1995-04-26

1997-07-15

Tran, Minh-Loan

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Combined with field effect transistor

257144, 257147, 257153, 257170, H01L 2974

Patent

active

056486650

ABSTRACT:
A P.sup.+ layer is formed on the lower surface of an N.sup.- substrate, and recesses are defined in the upper surface of the N.sup.- substrate. Then, P.sup.+ gate regions and bottom gate regions are formed in side walls and bottoms of the recesses. The N.sup.- substrate and an N.sup.- substrate are ultrasonically cleaned to remove impurities therefrom, then cleaned by pure water, and dried by a spinner. Then, while lands on the upper surface of the N.sup.- substrate are being held against the surface of the N.sup.- substrate, the N.sup.- substrate are joined to each other by heating then at 800.degree. C. in a hydrogen atmosphere.

REFERENCES:
patent: 4528745 (1985-07-01), Muraoka et al.
patent: 5153695 (1992-10-01), Gobrecht et al.
J. Nishizawa "High-Power Vertical Joint FET With Triode Characteristrics" Nikkei Electronics, vol. 1971. 9. 27 pp. 50-51, with English-Language Translation, Sep. 1971.
J. Nishizawa et al. "Field-Effect Transistor Versus Analog Transistor (Static Induction Transistor)", IEEE Trans. on Electron Devices, vol. 22 No. 4, Apr. 1975, pp. 185-197.
J. Nishizawa et al, "Static Induction Thyristor", Rev. de Physiquee Appliquee, TOME 13, Dec. 1978, pp. 725-728.
J. Nishizawa et al. "Effects of Gate Structure on Static Induction Thyristor", Tech. Dig. 1980 IEDMA, 1980 pp. 658-661.
J. Nishizawa et al, "Analysis of Characteristic of Static Induction Thyristor", Tech. Res. Report Electr., Comm. Soc., ED81-84 (1981) PPL 31-38, with Engl. Trans.
J. Nishizawa et al. "Static Induction Thyristor", Tech. Res. Report, Electr. Comm. Soc. ED81-7 (1981) pp. 49-55, with English -language Translation.

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