Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Patent
1997-03-27
1999-09-14
Everhart, Caridad
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
257773, H01L 2348
Patent
active
059527234
ABSTRACT:
A semiconductor device has a multilevel interconnection structure that includes an insulating interlayer formed on a lower wiring layer, a semiconductor substrate, and at least one via hole. The via plug partially fills the via hole, and the upper surface of the via plug may have a convex shape or a surface of the lower wiring layer at a bottom of the via hole may have a concave shape. Where two via holes are present, one via plug substantially fills the shallowest via hole, and partially fills the deepest via hole. The upper wiring layer may be formed over the via plug to fill a remaining portion of the via hole not filled by the via plug.
REFERENCES:
patent: 4640737 (1987-02-01), Nagasaka et al.
patent: 4666737 (1987-05-01), Gimpelson et al.
patent: 4924295 (1990-05-01), Kuecher
patent: 4970176 (1990-11-01), Tracey et al.
patent: 5006484 (1991-04-01), Harada
patent: 5043299 (1991-08-01), Chang et al.
patent: 5151305 (1992-09-01), Matsumoto et al.
patent: 5179042 (1993-01-01), Mikoshiba et al.
patent: 5234864 (1993-08-01), Kim et al.
patent: 5250465 (1993-10-01), Lizuka et al.
patent: 5288665 (1994-02-01), Nulman
patent: 5305519 (1994-04-01), Yamamoto et al.
patent: 5316972 (1994-05-01), Mikoshiba et al.
patent: 5360524 (1994-11-01), Hendel et al.
patent: 5374592 (1994-12-01), Mac Naughton et al.
patent: 5383970 (1995-01-01), Asaba et al.
patent: 5418187 (1995-05-01), Miyanaga et al.
patent: 5429710 (1995-07-01), Akiba et al.
patent: 5470792 (1995-11-01), Yamada
patent: 5482893 (1996-01-01), Okabe et al.
patent: 5486492 (1996-01-01), Yamamoto et al.
patent: 5633201 (1997-05-01), Choi
F.S. Chen, et al. "Advanced Planarized Aluminum Metallization Process" Adv. Metallization and Processing for Semicond. Dev. and Circuits II Symp. p. 617-22, 1992.
S. Wolff, et al., Jun. 1991 Proc. 8th Internat. IEEE VLSI Multilevel Interconnect. Conf. "Multilevel Interconnects Using Al CVD" p. 307.
Amazawa et al., Via Plug Process Using Selective CVD Aluminum for Multilevel Interconnection, Dec. 1991, pp. 265-268.
Hariu et al., The Properties of Al-Cu/Ti Films Sputter Deposited at Elevated Temperatures and High DC Bias, 1989, pp. 210-214.
Chen et al., Planarized Aluminum Metallization for Sub-0,5.mu.m CMOS Technology, 1990, pp. 51-54.
Park et al., Al-PLAPH (Aluminum-Planarization by Post-Heating) Process for Planarized Double Metal CMOS Applications Jun. 1991, pp. 326-328.
Yamamoto et al., Reliable Tungsten Encapsulated A1-Si Interconnects For Submicron Multilevel Interconnection, 1987, pp. 205-208.
Hiroshi Nishimura et al. Reliable Submicron Vias Using Aluminum Alloy High Temperature Sputter Filling VMIC Conf. (Jun. 11-12, 1991) pp. 170-176.
Katagiri Tomoharu
Kawano Yumiko
Kondoh Eiichi
Ohta Tomohiro
Takeyasu Nobuyuki
Everhart Caridad
Kawasaki Steel Corporation
LandOfFree
Semiconductor device having a multilevel interconnection structu does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having a multilevel interconnection structu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a multilevel interconnection structu will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1512566