Patent
1984-06-15
1986-10-21
James, Andrew J.
357 72, 357 54, 357 84, 357 4, H01L 2348
Patent
active
046188789
ABSTRACT:
A semiconductor device having a multilayer wiring structure which comprises a semiconductor substrate, a first wiring layer deposited on said substrate, and a second wiring layer deposited on said first wiring layer with insulating layers disposed therebetween, wherein the insulating interlayer consists of an inorganic insulating layer and a polyimide-based resin film overlying the inorganic insulating layer. The thickness ratio of the polyimide-based resin film to the inorganic insulating film ranges from 0.1 to 0.5. A method of manufacturing a semiconductor device of a multilayer wiring structure wherein an opening is formed in the insulating interlayer to have a small step.
REFERENCES:
patent: 3926914 (1975-12-01), Miyadera et al.
patent: 4472726 (1984-09-01), DiMaria et al.
patent: 4507333 (1985-03-01), Baise et al.
Mukai et al, "Planar Multilevel Interconnection Technology Employing a Polyimide," IEEE Jour. of Solid-State Circuits, vol. SC-13, No. 4, Aug. 1978, pp. 462-467.
Alcorn et al, "Self-Aligned Silicon Nitride-Polyimide Double Step Via Hole," IBM Tech. Discl. Bull., vol. 27, No. 7A, Dec. 1984, pp. 3990-3993.
Abe Masahiro
Ajima Takashi
Aoyama Masaharu
Yonezawa Toshio
James Andrew J.
Kabushiki Kaisha Toshiba
Mintel William
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