Semiconductor device having a multilayer wiring structure...

Details Semiconductor device having a multilayer wiring structure... Semiconductor device having a multilayer wiring structure...

2001-01-10

2002-11-05

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S768000, C438S622000

Reexamination Certificate

active

06476491

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a multilayer wiring structure, and particularly to a semiconductor device having a multilayer wiring structure and pad electrodes protected from corrosion, and a process for fabricating the same.
In semiconductor devices having multilayer wiring structures, wiring formed from aluminum-based alloys has been widely used. In such multilayer wiring, in general, pad electrodes are formed on the wiring on the uppermost layer, and external terminals are electrically connected to the pad electrodes through bonding wires or the like.
Recently, to achieve high speed and high performance of semiconductor devices, there is a tendency to use wiring formed from an alloy comprising, as a main component, copper which has low resistance and high reliability, so as to decrease wiring delay (or wiring resistance) or to increase the permissible current density of wiring.
FIGS. 20A
to
20
L show the steps of fabricating a semiconductor device using copper for wiring.
Referring to
FIG. 20A
, first, a semiconductor element
6
such as an MOS transistor comprising an insulating layer
2
for isolating the element, a gate-insulating layer
3
, gate electrodes
4
and an impurity-diffusion layer
5
is formed on a semiconductor substrate
1
. Then, an underlying insulating film
51
is deposited over a whole surface of the semiconductor element
6
by the thermal chemical vapor deposition process (thermal-CVD) or the plasma chemical vapor deposition process (plasma CVD). The underlying insulating film
51
has a three-layer structure which comprises an insulating layer
51
a
composed of a silicon oxide layer or a silicon oxide layer containing impurities such as phosphorous (P) and boron (B), a silicon nitride layer
51
b
serving to stop etching in the course of forming a wiring groove, and an insulating layer
51
c
such as a silicon oxide layer for forming the wiring groove.
Next, as shown in
FIG. 20B
, a contact hole
52
and a first wiring groove
53
are formed at predetermined positions on the underlying insulating film
51
by photolithography and etching. In this stage, the silicon nitride layer
51
b
has a high etching selective ratio with respect to the silicon oxide layer
51
c
, and thus serves as the stopper layer in the step of forming the first wiring groove
53
.
Next, as shown in
FIG. 20C
, a barrier metal layer
54
a
and a tungsten (W) layer
54
b
are deposited on the overall surface to fill the contact hole
52
and the first wiring groove
53
. As the barrier metal layer
54
a
, for example, a laminated film of a titanium (Ti) layer with a thickness of 10 to 50 nm and a titanium nitride (TiN) layer with a thickness of 50 to 100 nm is used to achieve good ohmic contact with the impurity-diffusion region
5
of the semiconductor device
6
.
Next, as shown in
FIG. 20D
, the tungsten layer
54
b
and the barrier metal layer
54
a
except for the contact hole
52
and the first wiring groove
53
are removed by chemical mechanical polishing (hereinafter referred to as CMP) using a hydrogen peroxide-based alumina abrasive so as to form a first buried metal wiring layer
54
which has a thickness of about 100 to about 300 nm.
Next, as shown in
FIG. 20E
, a first interlayer insulating film
55
having a three-layer structure consisting of an insulating layer
55
a
of a silicon oxide or the like, a silicon nitride layer
55
b
and an insulating layer
55
c
of a silicon oxide or the like is deposited on the surface of the first metal wiring layer
54
in the same manner as in FIG.
20
B. Subsequently, a first via hole
56
and a second wiring groove
57
are formed at predetermined positions on the first interlayer insulating film
55
by photolithography and etching.
Next, as shown in
FIG. 20F
, an underlying layer
58
a
and copper layers
58
b
and
58
c
are deposited on the overall surface so as to fill the first via hole
56
and the second wiring groove
57
. The underlying layer
58
a
serves to prevent the copper from diffusing into the ambient insulating layer of silicon oxide or the like. As the underlying layer
58
a
, generally, a tantalum (Ta) layer, a tantalum nitride (TaN) layer, a lamination (TaN/Ta) of tantalum and tantalum nitride layers, a titanium nitride layer (TiN), a lamination (TiN/Ti) of a titanium layer and a titanium nitride layer or the like is used.
Further, a copper seed layer
58
b
is deposited on the overall surface as an underlying layer for electrolytic plating, and then, a copper plating layer
58
c
is deposited on the overall surface by the electrolytic plating process using a plating solution containing, for example, copper sulfate as a main component.
Next, as shown in
FIG. 20G
, the copper layers
58
c
and
58
b
and the underlying layer
58
a
except for the first via hole
56
and the second wiring groove
57
are removed by CMP to form a second buried metal wiring layer
58
. The thickness of the second metal wiring layer
58
is, for example, about 300 to about 500 nm.
Next, as shown in
FIG. 20H
, a second interlayer insulating film having a four-layer structure consisting of a silicon nitride layer
59
a
for preventing copper from diffusing, an insulating layer
59
b
of silicon oxide or the like, a silicon nitride layer
59
c
and an insulating layer
59
d
of silicon oxide or the like is formed on the surface of the second metal wiring layer.
58
. Subsequently, a second via hole
60
and a third wiring groove
61
are formed at predetermined positions on the second interlayer insulating film
59
by photolithography and etching.
Similarly, an underlying layer
62
a
and copper layers
62
b
and
62
c
are deposited on the overall surface so as to fill the second via hole
60
and the third wiring groove
61
, and then, the copper layers
62
c
and
62
b
and the underlying layer
62
a
except for the second via hole
60
and the third wiring groove
61
are removed by CMP to form a third buried metal wiring layer
62
.
Next, as shown in
FIG. 20I
, a third interlayer insulating film
63
having a four-layer structure consisting of a silicon nitride layer
63
a
, an insulating layer
63
b
of silicon oxide or the like, a silicon nitride layer
63
c
and an insulating layer
63
d
of silicon oxide or the like is deposited on the surface of the third metal wiring layer
62
in the same manner as in FIG.
20
H. Subsequently, a third via hole
64
and a fourth wiring groove
65
are formed at predetermined positions on the third interlayer insulating film
63
by photolithography and etching. Then, an underlying layer
66
a
and copper layers
66
b
and
66
c
are deposited on the overall surface so as to fill the above hole and groove. Then, unnecessary portions of the copper layers
66
c
and
66
b
and the underlying layer
66
a
are removed by CMP so as to form a fourth buried metal wiring layer
66
.
In this connection, the fourth and the fifth metal wiring layers are used as long-distance wiring and a power source line, and therefore have higher thickness as compared with the underlying first to third metal wiring layers.
Next, as shown in
FIG. 20J
, a forth interlayer insulating film
67
having a four-layer structure consisting of a silicon nitride layer
67
a
, an insulating layer
67
b
of silicon oxide or the like, a silicon nitride layer
67
c
and an insulating layer
67
d
of silicon oxide or the like is deposited on the forth metal wiring layer
66
in the same manner as in FIG.
20
I. Subsequently, a forth via hole
68
and a fifth wiring groove
69
are formed at predetermined positions on the forth interlayer insulating film
67
, and then, an underlying layer
70
a
and copper layers
70
b
and
70
c
are deposited on the overall surface to fill the above hole and the above groove. Then, unnecessary portions of the copper layers
70
c
and
70
b
and the underlying layer
70
a
are removed by CMP to form a fifth buried metal wiring layer
70
.
Usually, a pad electrode
71
for use in connecting an external terminal is co

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