Semiconductor device having a multilayer leadframe with full pow

Details Semiconductor device having a multilayer leadframe with full pow Semiconductor device having a multilayer leadframe with full pow

1991-12-19

1993-06-15

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

257691, H01L 2348, H01L 2350

Patent

active

052201953

ABSTRACT:
A semiconductor device (10) has a multilayer leadframe (14) with two full voltage planes, specifically an upper voltage plane (16) and a lower voltage plane (18). A semiconductor die (12) is mounted to the upper voltage plane. Bond pads (13) of the die are electrically coupled to appropriate leads (20a, 20b, and 20c) using conductive wires (22). Upper voltage plane (16) is provided with at least one opening (28) to allow passage of a conductive wire through the opening in order to electrically couple a bond pad or a lead to lower voltage plane (18). The voltage planes are attached to the leadframe using welded conductive tabs (24), an electrically insulating adhesive layer (26), or both.

REFERENCES:
patent: 4445271 (1984-05-01), Grabbe
patent: 4835120 (1989-05-01), Mallik et al.
patent: 4891687 (1990-01-01), Mallik et al.
patent: 5032895 (1991-07-01), Horiuchi et al.
patent: 5053921 (1991-10-01), Nelson et al.
patent: 5089878 (1992-02-01), Lee
patent: 5089881 (1992-02-01), Panicker
"Thermal Characteristics of Single and Multilayer High Performance PQFP Packages," by M. Aghazadeh et al., IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 13, No. 4, Dec. 1990, pp. 975-979.

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