Semiconductor device having a multilayer interconnection...

Details Semiconductor device having a multilayer interconnection... Semiconductor device having a multilayer interconnection...

2006-11-28

2006-11-28

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S774000, C438S622000, C438S629000

Reexamination Certificate

active

07141881

ABSTRACT:
A semiconductor device includes an interconnection structure in which via-plug density is higher in an upper layer part than a lower layer part, wherein the peeling of the lower via-plugs at the time of formation of the upper-via-plugs is avoided by restricting the density of the upper s, defined for a unit area having a size of 50–100 μm for each edge, to be 60% or less.

REFERENCES:
patent: 2003/0155642 (2003-08-01), Davis et al.
patent: 11-233517 (1999-08-01), None
patent: 2002-299342 (2002-10-01), None
patent: 2003-142485 (2003-05-01), None
Fuhan Liu; Sundaram, V.; Mekala, S.; White, G.; Sutter, D.A.; Tummala, R.R.; Fabrication of Ultra-Fine Line Circuits on PWB Substrates; IEEE Electronic Components and Technology Conference, 2002. Proceedings. 52nd; May 28-31, 2002 pp. 1425-1431.

Affiliated with

Also associated with

Rating

Semiconductor device having a multilayer interconnection... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device having a multilayer interconnection..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a multilayer interconnection... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3670407