Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2007-08-13
2009-08-18
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S774000, C257S777000
Reexamination Certificate
active
07576421
ABSTRACT:
A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected to an external circuit. Each source electrode, a corresponding signal electrode and a corresponding ground electrode are arranged adjacent to one another in this order to reduce electromagnetic noise during operation of the DRAM chip.
REFERENCES:
patent: 5619465 (1997-04-01), Nomura et al.
patent: 6037677 (2000-03-01), Gottschall et al.
patent: 6242814 (2001-06-01), Bassett
patent: 6421281 (2002-07-01), Suzuki
patent: 10261009 (2003-07-01), None
patent: 0617466 (1994-09-01), None
patent: 5-41463 (1993-02-01), None
patent: 10-163411 (1998-06-01), None
patent: 2002-305283 (2002-10-01), None
patent: 2003-60053 (2003-02-01), None
Elpida Memory Inc.
Rao Steven H
Weiss Howard
Young & Thompson
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