Semiconductor device having a multi-layer channel structure

Details Semiconductor device having a multi-layer channel structure Semiconductor device having a multi-layer channel structure

1994-12-22

1996-12-17

Nelms, David C.

Static information storage and retrieval

Floating gate

36518517, 36518524, G11C 1140

Patent

active

055860737

ABSTRACT:
A non-volatile semiconductor memory cell has a channel layer with a two-layered structure including a surface channel layer and a buried channel layer. The operation of reading out "1" level data or "0" level data from the memory cell is effected by using only the buried channel layer and based on whether the conductivity type of the buried layer is inverted or not. The operation of writing "0" level data is effected by using both of the surface channel layer and the buried channel layer, simultaneously inverting the conductivity types of the surface channel layer and the buried channel layer, and passing a current into the inverted layer to generate hot electrons.

REFERENCES:
patent: 4467452 (1984-08-01), Saito et al.
patent: 5243210 (1993-09-01), Naruke
H. Oda et al., "FLASH Memory Cell Using Buried Channel Type n-MOSFET", Extended Abstracts (The 40th Spring Meeting, 1993) The Japan Society of Applied Physics and Related Societies, No. 2, p. 741, dated Mar. 29, 1993.
H. Oda et al; Extended Abstracts (The 40th Spring Meeting, 1993) The Japan Society of Applied Physics and Relates Societies No. 2, p. 741, FLASH Memory Cell Using Buried Channel Type n-MOSFET, H. dated Mar. 29, 1993, discloses Flash memory cell in which the difference of the electrical condition of the channel area between the read operation and the program operation is not restricted.
S. M. Sze, Physics of Semiconductor Devices, pp. 464-469, .sctn.8.3.3. "Buried-Channel Devices", 1981.

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